[SI-LIST] : layer stackup

About this list Date view Thread view Subject view Author view

From: Aric Hadav ([email protected])
Date: Mon Dec 11 2000 - 03:11:08 PST


I'm looking for some help on deciding on my board layer stackup.
my design has ~20K pads and it must fit into a standard 6U board, 1.6 mm
the board thickness CAN NOT be changed.

the PCB layout guy told me that the design can only fit into a minimum of 14
layers stack up,
with a 3-4 mil core and preg thickness, as described below:
1. CS
2. sig1
3. VCC1V8
4. sig2
5. sig3 (ctrl impedance).
6. sig4
7. GND
8. sig5
9. sig6 (ctrl impedance).
10. sig7
11. VCC3V
12. sig8
13. sig9
14. PS

now, this looks some what strange to me since layers 5 & 9 aren't adjacent
to a PWR/GND
plane, since one should always try that a signal layer will be close to
reference plane.
now, in order to reduce the crosstalk between layers 4 to 6 or 8 to 10 he
suggested to route the
signals not horizontally and vertically but
layers 4, 8 - 45 degrees.
layers 5, 9 - vertical or horizontal.
layers 6, 10 - 135 degrees.
has anyone routed this way ? did it work ok ?
the signal clocks will be routed in layers 5 and 9 which supposed to be
control impedance. is it ok ?
has anyone has other suggestions to the layer stuckup?


        Aric Hadav
        Hardware Design Engineer
        [email protected]

**** To unsubscribe from si-list or si-list-digest: send e-mail to
[email protected] In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu

About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:30:24 PDT