[SI-LIST] : D/W vs. S/H

About this list Date view Thread view Subject view Author view

From: Loyer, Jeff W (jeff.w.loyer@intel.com)
Date: Wed Nov 29 2000 - 12:54:52 PST


Doug's query brought up a related question to my feeble mind...

Is there any reason to specify distance between traces relative to their
width? As far as I know, the most critical dimensions to consider are: 1)
distance between the edges of two traces, relative to 2) distance between
the trace and its ground plane(s). The width of the conductor is not a
significant factor, unless you're using center-to-center separation, where
you'll have to take into account the width. I don't understand why we
wouldn't specify S/H instead of D/W (see below).

______________________________________________________ GND
      ^
      |
     (H)
      |
      v
    ___________ <--- (S) ---> ___________ Signals traces
    <-- (W) -->
         <---------- (D) ---------->

Jeff Loyer
(253) 371-8093

-----Original Message-----
From: Doug Hopperstad [mailto:doug.hopperstad@qlogic.com]
Sent: Wednesday, November 29, 2000 12:27 PM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : RE: Crosstalk Bus spacing

When determining the minimum spacing between traces on a digital bus, is it
best to setup the three traces as follows:(The design is using a stripline)

"A": Aggressor trace
"V": Victim trace
"A": Aggressor trace

------------------------------------------------------- Ground Plane layer
------(A)------ ------(V)------ ------(A)------ Trace layer, 0.5
ounce.
------------------------------------------------------- Ground Plane layer

Should both Aggressors be in-phase with each other or should one of them be
inverted to get the worst case crosstalk. I am simulating with both
applications and getting much more crosstalk on the victim trace when both
aggressors are in-phase.

The clock edge rate is 950pS and the trace width is set at w = 5 mils. The
Plane to trace layer spacing is 6.5 mils. This provides a nice 50 ohm trace
impedance.
The distance between traces is set at 5 mils (1w). I have been playing with
2w in the simulations as well.

Is it traditional to set the trace-to-trace spacing on the bus traces, i.e.
bits(0:x) for example, at 1w the trace width. The bus-to-adjacent traces
have been set for 2w spacing. The clock spacing is set for a 3w minimum.

Doug Hopperstad

**** To unsubscribe from si-list or si-list-digest: send e-mail to
majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****

**** To unsubscribe from si-list or si-list-digest: send e-mail to
majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:30:18 PDT