Re: [SI-LIST] : Plane Splits Inspection

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From: Ritchey Lee (leeritchey@earthlink.net)
Date: Wed Nov 22 2000 - 09:37:41 PST


That is exactly what happens. Trick is to make sure that there is a
good
plane underlying the split. This is usually the ground plane of a power
plane subsystem.

Lee

Mike LaBonte wrote:

> Patrick,
>
> Would you agree that your nearby solid plane is basically a large,
> distributed capacitor, performing essentially the same function
> as Abe's stitched capacitors? Admittedly a return current at split
> plane A must pass through the dielectric to the solid plane, across
> a little bit of solid plane, and then back through the dielectric
> to split plane B. But it does form a capacitive coupling that is
> available everywhere; therefore no need to calculate capacitor
> placement. I have not considered capacitance magnitude differences,
> however.
>
> A separate discussion could be held on what happens to the currents
> induced in the solid plane.
>
> Mike LaBonte
> Cadence
>
> "Zabinski, Patrick J." wrote:
> >
> > Abe,
> >
> > In the general sense, I agree with your comments. However, I
> > have found exceptions.
> >
> > As an example, if your board cross section looks something like:
> >
> > --- Microstrip
> > Dielectric
> > -------------- Split Plane
> >
> > then the statements you make below are true.
> >
> > However, through empirical experimentation, we have found that
> > many of the issues you discuss (crosstalk, discontinuity, etc.)
> > can be drastically reduced. By inserting a solid plane under the
> > split plane, like:
> >
> > --- Microstrip
> > Dielectric
> > -------------- Split Plane
> > "Thin" dielectric
> > -------------- Solid Plane
> >
> > we have noticed dramatic improvements in performance. We have not
> > taken our studies to the point of being able to engineer the
> > effects of the solid plane, but by inserting a solid plane under the
> > splits, much of what you discuss is no longer an issue (we did not
> > test for EMI, but I suspect it improves as well).
> >
> > You also mention the stitching capacitors. We have found them to
> > be useful. However, what I did not predict is the frequency
> > (spacing) in which you must place them. Using one test board,
> > we placed an ideal stitching capacitor (shorting bar) across the split,
> > and slid the capacitor along the split. We then injected signals
> > of various edge rates ranging from 35 psec to 1 nsec. Prior
> > to making the measurements, I predicted that there would be
> > a relationship between the edge rate and how far the cap could be
> > away from the trace. What I found was that the regardless of
> > edge rate, the stitching cap needed to be within 2 mm of the
> > trace! This was quite unexpected.
> >
> > Most members of this list should be well aware of the potential
> > issues associated with splits (it's been discussed SEVERAL
> > times), but it does seem like we haven't quite explored
> > the entire issue quite yet.
> >
> > Pat
> >
> > > Dear Scholars:
> > >
> > > It is well known that when a high-speed signal crosses a slot
> > > of an adjacent reference Ground or Power plane, several
> > > undesirable effects can occur. For instance, a disturbance of
> > > return current path takes place which can cause a glitch,
> > > increased crosstalk and EMI radiation. The rule that routing
> > > of high-speed nets over voids or cuts of neighboring plane
> > > layers must be avoided is firmly established in the SI
> > > literature. Yet, the complexity of modern high speed designs
> > > imposes many violations of above guideline.
> > >
> > > To make matters more complicated, many simulation programs
> > > assume continuous Ground and Power planes and do not
> > > accurately take into account effects of plane discontinuities
> > > on the return current path. It is therefore, important to
> > > visually inspect a PCB database for the signals crossing
> > > plane slots (and voids), before generating the Gerber files
> > > and releasing the design for fabrication.
> > >
> > > Figure 1 illustrates several concepts associated with such
> > > examination. A section of a power plane is shown having gap G
> > > (due to presence of multiple powers) and several traces (T1,
> > > T2, T3 and T4) of an adjacent signal layer which are routed
> > > over the splits. C1 and C2 represent two stiching
> > > capacitors. In this example the gap width is 20 mils.
> > > Smaller widths (such as 10 mils) can be preferable since the
> > > break should be as narrow as feasible. Majority of crossings
> > > occurs at 90 degree angle with respect to axes of slot in
> > > order to minimize the segment length over the void. Some of
> > > the traces contain serpentines but are routed to pass
> > > boundaries only once. Stiching capacitors are utilized to
> > > minimize undesirable effects of the cuts.
> > >
> > > Certain rules of thumb have been formulated for determination
> > > of the required number and values of stiching capacitors; an
> > > example follows:
> > >
> > > For every five traces which cross a plane slot, insert
> > > approximately one or more capacitors within each 0.250 in.
> > > 0.01uF is an acceptable value for "stiching" capacitors,
> > > though it is preferable to mix several
> > > 2251 Lawson Lane
> > > Santa Clara, CA 95054
> > >
> > >
> > >
> > >
> > >
> >
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