**From:** Mike LaBonte (*[email protected]*)

**Date:** Thu Nov 09 2000 - 06:15:37 PST

**Next message:**Gaboian, Jerry: "[SI-LIST] : Routing Differential Pairs as 100 differentially Vs individually 50 ohm lines"**Previous message:**Zabinski, Patrick J.: "RE: [SI-LIST] : Plane Splits Inspection"**In reply to:**Zabinski, Patrick J.: "RE: [SI-LIST] : Plane Splits Inspection"**Next in thread:**Chris Padilla: "Re: [SI-LIST] : Plane Splits Inspection"**Reply:**Chris Padilla: "Re: [SI-LIST] : Plane Splits Inspection"**Reply:**Ritchey Lee: "Re: [SI-LIST] : Plane Splits Inspection"

Patrick,

Would you agree that your nearby solid plane is basically a large,

distributed capacitor, performing essentially the same function

as Abe's stitched capacitors? Admittedly a return current at split

plane A must pass through the dielectric to the solid plane, across

a little bit of solid plane, and then back through the dielectric

to split plane B. But it does form a capacitive coupling that is

available everywhere; therefore no need to calculate capacitor

placement. I have not considered capacitance magnitude differences,

however.

A separate discussion could be held on what happens to the currents

induced in the solid plane.

Mike LaBonte

Cadence

"Zabinski, Patrick J." wrote:

*>
*

*> Abe,
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*>
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*> In the general sense, I agree with your comments. However, I
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*> have found exceptions.
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*>
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*> As an example, if your board cross section looks something like:
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*>
*

*> --- Microstrip
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*> Dielectric
*

*> -------------- Split Plane
*

*>
*

*> then the statements you make below are true.
*

*>
*

*> However, through empirical experimentation, we have found that
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*> many of the issues you discuss (crosstalk, discontinuity, etc.)
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*> can be drastically reduced. By inserting a solid plane under the
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*> split plane, like:
*

*>
*

*> --- Microstrip
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*> Dielectric
*

*> -------------- Split Plane
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*> "Thin" dielectric
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*> -------------- Solid Plane
*

*>
*

*> we have noticed dramatic improvements in performance. We have not
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*> taken our studies to the point of being able to engineer the
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*> effects of the solid plane, but by inserting a solid plane under the
*

*> splits, much of what you discuss is no longer an issue (we did not
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*> test for EMI, but I suspect it improves as well).
*

*>
*

*> You also mention the stitching capacitors. We have found them to
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*> be useful. However, what I did not predict is the frequency
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*> (spacing) in which you must place them. Using one test board,
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*> we placed an ideal stitching capacitor (shorting bar) across the split,
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*> and slid the capacitor along the split. We then injected signals
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*> of various edge rates ranging from 35 psec to 1 nsec. Prior
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*> to making the measurements, I predicted that there would be
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*> a relationship between the edge rate and how far the cap could be
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*> away from the trace. What I found was that the regardless of
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*> edge rate, the stitching cap needed to be within 2 mm of the
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*> trace! This was quite unexpected.
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*>
*

*> Most members of this list should be well aware of the potential
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*> issues associated with splits (it's been discussed SEVERAL
*

*> times), but it does seem like we haven't quite explored
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*> the entire issue quite yet.
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*>
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*> Pat
*

*>
*

*> > Dear Scholars:
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*> >
*

*> > It is well known that when a high-speed signal crosses a slot
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*> > of an adjacent reference Ground or Power plane, several
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*> > undesirable effects can occur. For instance, a disturbance of
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*> > return current path takes place which can cause a glitch,
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*> > increased crosstalk and EMI radiation. The rule that routing
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*> > of high-speed nets over voids or cuts of neighboring plane
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*> > layers must be avoided is firmly established in the SI
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*> > literature. Yet, the complexity of modern high speed designs
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*> > imposes many violations of above guideline.
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*> >
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*> > To make matters more complicated, many simulation programs
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*> > assume continuous Ground and Power planes and do not
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*> > accurately take into account effects of plane discontinuities
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*> > on the return current path. It is therefore, important to
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*> > visually inspect a PCB database for the signals crossing
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*> > plane slots (and voids), before generating the Gerber files
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*> > and releasing the design for fabrication.
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*> >
*

*> > Figure 1 illustrates several concepts associated with such
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*> > examination. A section of a power plane is shown having gap G
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*> > (due to presence of multiple powers) and several traces (T1,
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*> > T2, T3 and T4) of an adjacent signal layer which are routed
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*> > over the splits. C1 and C2 represent two stiching
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*> > capacitors. In this example the gap width is 20 mils.
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*> > Smaller widths (such as 10 mils) can be preferable since the
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*> > break should be as narrow as feasible. Majority of crossings
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*> > occurs at 90 degree angle with respect to axes of slot in
*

*> > order to minimize the segment length over the void. Some of
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*> > the traces contain serpentines but are routed to pass
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*> > boundaries only once. Stiching capacitors are utilized to
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*> > minimize undesirable effects of the cuts.
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*> >
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*> > Certain rules of thumb have been formulated for determination
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*> > of the required number and values of stiching capacitors; an
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*> > example follows:
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*> >
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*> > For every five traces which cross a plane slot, insert
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*> > approximately one or more capacitors within each 0.250 in.
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*> > 0.01uF is an acceptable value for "stiching" capacitors,
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*> > though it is preferable to mix several
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*> > 2251 Lawson Lane
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*> > Santa Clara, CA 95054
*

*> >
*

*> >
*

*> >
*

*> >
*

*> >
*

*>
*

*> **** To unsubscribe from si-list or si-list-digest: send e-mail to
*

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*

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**Next message:**Gaboian, Jerry: "[SI-LIST] : Routing Differential Pairs as 100 differentially Vs individually 50 ohm lines"**Previous message:**Zabinski, Patrick J.: "RE: [SI-LIST] : Plane Splits Inspection"**In reply to:**Zabinski, Patrick J.: "RE: [SI-LIST] : Plane Splits Inspection"**Next in thread:**Chris Padilla: "Re: [SI-LIST] : Plane Splits Inspection"**Reply:**Chris Padilla: "Re: [SI-LIST] : Plane Splits Inspection"**Reply:**Ritchey Lee: "Re: [SI-LIST] : Plane Splits Inspection"

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