RE: [SI-LIST] : Connector pin pwr/gnd ratio

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From: Peterson, James F (FL51) ([email protected])
Date: Mon Nov 13 2000 - 13:43:43 PST

The original question was meant to be:

On my board (CMOS logic), I have 85 connector pins allotted for 3.3v, 2.5v
and gnd.
How would you distribute? and why?

Would you do 25% for 3.3v, 25% for 2.5v, and 50% for gnd? (which is a
component approach, but maybe not a board approach.)

Would you minimize the pwr pins and maximize the gnd pins? if so, why?
(don't we have return currents flowing in both.)

all inputs and opinions are welcome and appreciated.

Jim

-----Original Message-----
From: Charles Grasso [mailto:[email protected]]
Sent: Monday, November 13, 2000 4:25 PM
To: Peterson, James F (FL51); [email protected]
Subject: Re: [SI-LIST] : Connector pin pwr/gnd ratio

The allocation of grounds with respect to any number of signals is mainly
based
on rise time (hence frequency content). That is to say the faster the rise
time the
more grounds you need - the asymptote being a solid "bar" connection found
in many impedace controlled connectors.

----- Original Message -----
From: "Peterson, James F (FL51)" <[email protected]>
To: <[email protected]>
Sent: Monday, November 13, 2000 6:57 AM
Subject: [SI-LIST] : Connector pin pwr/gnd ratio

> Hello,
>
> I'm looking for some information on what the pwr/gnd ratio should be for a
> board's connector. (I know there is something in the archives, but I
> couldn't find it.)
>
> Someone said a rule of thumb is a 3 to 1 ratio, but I'm not sure what that
> is based on.
>
> So let's say for example I have 85 connector pins for 3.3v, 2.5v and gnd.
> How would you distribute? and why?
>
> thanks
> Jim
> > Jim Peterson
> > [email protected]
> > Honeywell Space Systems
> > M/S 934-5
> > 13350 U.S. Hwy 19 N.
> > Clearwater FL, 33764-7290
> > Office : 727-539-2719
> > Fax : 727-539-2183
>
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