From: Doug McKean (firstname.lastname@example.org)
Date: Mon Nov 13 2000 - 14:31:31 PST
"Peterson, James F (FL51)" wrote:
> The original question was meant to be:
> On my board (CMOS logic), I have 85 connector pins allotted for 3.3v, 2.5v
> and gnd.
> How would you distribute? and why?
> Would you do 25% for 3.3v, 25% for 2.5v, and 50% for gnd? (which is a
> component approach, but maybe not a board approach.)
> Would you minimize the pwr pins and maximize the gnd pins? if so, why?
> (don't we have return currents flowing in both.)
> all inputs and opinions are welcome and appreciated.
Personally? I'd maximize gnd pins.
Reason? To create a sort of quasi
gnd shielding effect within the
connector. Let me illustrate ...
G = ground pin
P = power pin (doesn't matter if it's 3.3, 2.5, 5, ...)
G G G G G G
P G P G P
G G G G G G
Ideal configuration of course ...
Regards, Doug McKean
**** To unsubscribe from si-list or si-list-digest: send e-mail to
email@example.com. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:30:06 PDT