Re: [SI-LIST] : PCI speedway

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From: Michael Nudelman (mnudelman@tellium.com)
Date: Wed Sep 27 2000 - 06:15:53 PDT


I'll look up the name of the book I have at home; this is the best book for the PCI
design I ever saw and I used it in my design.

The PCI bus is fairly tolerant at 33MHz. I stretched it for almost 18 inches with
one north bridge and it worked reliably, though it was a necessity. If you can use a
"slave" bridge to cut the bus in half (again, if your bus becomes very long) - do
it.

The layout is simple - fairly uniform bus, no stubs; de-scewed clock, for which I
personally would recommend Cypress Robo-Clock drivers.

Advise: do put a test header for a digital analyzer on all PCI signals; PCI protocol
is fascinating and sometimes without analyzer you won't get far.

Mike.

liquadri@aethra.it wrote:

> Hi , Guy
>
> somebody can help me to looking for real example to PCI speedway layout and
> component placing ?
> I know the EDN article (november 1994) about this issue and the abstract to Star
> ?Hspice manual.
>
> thanks for your help
> Ciao Angelo
>
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