Re: [SI-LIST] : A few questions about specctraquest

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From: Lalit Shinde (lalit@cadence.com)
Date: Sat Aug 19 2000 - 16:31:21 PDT


Hi Aloke,

Here are answers to your questions (my appologies for wide distribution
I think there are more people interested. For others, please delete ...)

(i) You can use Auto model assignment capability on model assignment
    form to achieve this. Discrete components are identified based on
    certain Allegro properties. To setup your board correctly, it's
    always advisible to run through Allegro Setup Advisor which would
    correct any problems within board. This setup is required only
    once. Once you do it you would save a lot of time in these kind
    of questions.

(ii) I guess you are trying to simulate without the other board (in
     single board system). If you are using sigxplorer, you can extract,
     the net/topology and sprinkle dummy probe elements at all nodes
     in the circuit at which you want to view the waveform. You can also
     add drivers if they are missing. Within SPECCTRAQuest/Allegro, you
     can temporarily change pinuse on connector pins to be either IN or
     OUT based on whether signal is coming on board or going out of
     board, and then simulate. Remember to change the pinuse back to
     UNSPEC or run setup advisor.

(iii) This is where you can use sigxplorer to explore all possibilities
      on other board by simply adding required circuits to extracted
      net/topology.

(iv) There are ways to use spice connector models by including relevant
     portions into SingleLineCircuits and CoupledLineCircuits within dml.

Aloke Bhattacharya wrote:
>
> Hello all,
> I am a new user of the Cadence Specctraquest tool. I have a few
> questions about the tool:
> (i) For simulation, do I need the models for the passive components
> also? I thought that the tool would automatically extract the parameters
> and generate the .dml files for the passives(i.e. resistors and
> capacitors), but I find that it's doing that for only a few of them. I
> am working on a Allegro board file where the schematics was done in
> Concept-HDL. I don't understand why the tool is able to extract the
> models for only a few passive components, and not all of them. Is this
> extraction dependent upon some
> particular property(like CLASS, VALUE etc) associated with the part?
>
> (ii) Suppose a net/xnet is connected between an IC and a connector in
> the board. In this case, as the connector is a passive component, if the
> IC pin is a driver, there will not be any receiver on the net and if the
> IC pin is a receiver, there will not be any driver on the net. Hence, it
> looks like this net cannot be simulated. Is there any way by which I can
> simulate this net?
>
> (iii) Continuing the above question: suppose the connector mentioned
> above will be used to connect the current board to another board which
> is not yet designed. Hence, I cannot use designlink to simulate the
> connections between the boards. Is there any way to perform some
> preliminary simulations on the section between IC's and the connector of
> the current board so that we can do necessary layout changes in the
> current board without waiting for the other board layout to be finished?
> I have the schematics of the other board and the .dml models for the
> ICs, but not the board file.
>
> (iv)I find very difficult to get an IBIS model of a connector. In case
> the connector is used to connect two boards, the model is definitely
> required. How do you manage to get the IBIS model? Do you create the
> IBIS model yourself? If yes, can you give an idea of what are the
> parameters required and how to crate an IBIS/.dml model for a
> connector?
>
> Thanks in advance,
> With regards,
> Aloke
>
> --
> **********************************************************************
> * Aloke Bhattacharya, *
> * Senior Engineer-VLSI/System Design,
> * *
> * Wipro Infotech, *
> * Global R&D, *
> * 88, M.G. Road, 5th Floor, *
> * S.B. Towers, *
> * Bangalore- 560 001 , *
> * INDIA *
> * Tel : 91-80-5588422(Ext. 520) *
> * email: aloke.bhattacharya@wipro.com
> * *
> **********************************************************************
>
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-- 
Regards,
-Lalit.
978-262-6475.

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