RE: [SI-LIST] : Decoupling capacitors (again!)

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From: Don Major ([email protected])
Date: Sat Aug 19 2000 - 22:24:03 PDT


Beware of cheating physics: dielectrics which have a high dielectric
constant are also slow (wave propagation), so the portion of the plane
charge available to a given circuit node is reduced compared to using low
dielectric constant materials.

-----Original Message-----
From: [email protected]
[mailto:[email protected]]On Behalf Of Ray Anderson
Sent: Friday, August 18, 2000 3:27 PM
To: [email protected]
Subject: Re: [SI-LIST] : Decoupling capacitors (again!)

Earlier today Charles Grasso ([email protected]) posted a message about the
NCMS Buried Capacitance Project which in part read as follows:

>Hi - This would seem an excellent opportunity to appraise the community of
>the final stages of the NCMS Buried Capacitance project I was fortunate to
>be a part of.

>Fundamentally the research efforts are complete, a design guide written by
>UMR is (I think)complete and a final report is close to compellation.

>Richard Charbonneau & I would like to take this opportunity to remind the
>Community of a workshop on this subject that will include some of the
>who contributed to this research. Here is the title:

> The National Center for Manufacturing Sciences and Embedded Decoupling
> Capacitance Consortium
> August 21, 2000 NIST Campus Gaithersburg, Maryland. I have attached a
> copy of the flyer for your convenience.

        The flyer attachment he alluded to was deleted by the si-list mail server
        due to it's size. I have scraped the deleted bitsand bytes out of the
        bit-bucket and have posted them on the si-list archives web site.

        The flyer can be accesed by going to the si-list web site at


        and clicking on the EDC Conference link or you can get there directly at
        the following URL:


-Ray Anderson
Sun Microsystems

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