From: Greim, Michael ([email protected])
Date: Fri Aug 11 2000 - 08:00:32 PDT
Here's my 0.02
From my understanding, the various vendors will only
guarantee a switch at a differential voltage of 100mV.
Therefore, one wishes to have the time between these
switch points be as small as possible as this creates
an area of uncertainty where the input may switch or
not. Given temp, voltage and process an input may
switch anywhere within this region. As was pointed out
before, this is manefested as jitter across the three
corner domains. Therefore, the tighter the skew budget, the
quicker the transition through this region, the smaller
the jitter across PVT and the larger the eye.
MG
-----Original Message-----
From: David Haedge [mailto:[email protected]]
Sent: Friday, August 11, 2000 10:33 AM
To: [email protected]
Subject: Re: [SI-LIST] : LVDS Skew
Dear SIer's
Thanks to all for the response on this topic. It is much appreciated.
I am sitting here with a piece of paper and a transparency with
the rising and falling edges drawn on them as suggested by Scott
and have noticed something peculiar. Assuming that we are using
1.2 V as the offset voltage and 1.025 V and 1.375 V as the high and
low voltages, when the skew gets large enough, both sides of the
100 ohm termination resistor at the receiver are at the same
voltage for some time (until the other edge comes along.)
I looked at the LVDS spec and it states that the receiver differential
threshold is 100mV. If the receiver differential voltage is sitting
at 0mV for any length of time, what is the output state?
Is anybody familiar with the inner workings of these inputs?
Some of the responses so far indicate that the input will indeed
switch when the other side changes, but what are the ramifications
of the receiver input being at 0 mV for any amount of time?
David Haedge
Raytheon
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