From: David Haedge (firstname.lastname@example.org)
Date: Wed Aug 09 2000 - 14:31:13 PDT
I have a person concerned about 55ps of skew between the two traces
on an LVDS differential pair. The LVDS bus is running at 200MHz, a
5ns period. What negative effect on the system would occur if say,
there was a 100ps or even 200ps mismatch? Timing margins are
still within spec with even a 1ns mismatch. Some common mode
currents may be launched, but I think they would cause minimal
noise and not cause any circuit upsets. Has anybody seen problems
with LVDS signaling with >55ps diff pair line skew?
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