RE: [SI-LIST] : LVDS Skew

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From: Farrokh Mottahedin (Farrokh.Mottahedin@quantum.com)
Date: Wed Aug 09 2000 - 15:47:19 PDT


David,

Two questions come to mind: 1) Are you using single clock transition or
double clock transition? and, 2) Is this a point-to-point bus or a
multidrop bus? If you don't have to worry about noise and EMI, and your
timing is such that you can tolerate 1 ns mismatch, then you should have no
problems with 55 ps of pair skew. In SCSI Ultra 160 standard (160 MBytes/s,
double edge clocking), we have 6.25 ns setup and hold budgets. The 12 meter
cable and 15 other transceivers on the bus can introduce as much as 3 ns of
skew and still be within timing budgets.

          
Regards,

Farrokh Mottahedin

Quantum Corp.
500 McCarthy Blvd.
Milpitas, CA 95035
(408)324-7934
farrokh.mottahedin@quantum.com

-----Original Message-----
From: David Haedge [mailto:d-haedge@raytheon.com]
Sent: Wednesday, August 09, 2000 2:31 PM
To: si-list@silab.Eng.Sun.COM
Subject: [SI-LIST] : LVDS Skew

Dear SIer's:

I have a person concerned about 55ps of skew between the two traces
on an LVDS differential pair. The LVDS bus is running at 200MHz, a
5ns period. What negative effect on the system would occur if say,
there was a 100ps or even 200ps mismatch? Timing margins are
still within spec with even a 1ns mismatch. Some common mode
currents may be launched, but I think they would cause minimal
noise and not cause any circuit upsets. Has anybody seen problems
with LVDS signaling with >55ps diff pair line skew?

David Haedge
Raytheon

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