[SI-LIST] : SI opening at Atoga Systems

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From: Dan Bostan (dbostan@ix.netcom.com)
Date: Thu Jun 22 2000 - 23:15:55 PDT


Atoga Systems (a brand new start-up in optical networking) is looking for
experienced board designer engineers with significant expertise in signal
integrity (XTK and HSpice) and static timing analysis.
MSEE required.

Please contact Dan Bostan, ph # 408.248.7200/x109, e-mail dan@atoga.com.

-----Original Message-----
From: owner-si-list@silab.eng.sun.com
[mailto:owner-si-list@silab.eng.sun.com]On Behalf Of Bert Chan
Sent: Tuesday, May 23, 2000 9:03 AM
To: si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : SI opening at Intel

Sean -

I would like to be seriously considered for the
Subject Position.

I think I have all the qualifications required, except
an advanced knowleded of C++, which I believe can be
remedied by a brief and intensive application
training.

My resume follows.

Regards -

Bert

Bertram K.C. Chan, PhD,PE(California)
(408) 739-1068
bertchan@yahoo.com

=======================================================
               Bertram (Bert) K. C. Chan

    1534 Orillia Court, Sunnyvale, CA 94087-4435

Home & VoiceMail & FAX: (408) 739-1068

     E-Mail: bertchan@yahoo.com

PROFESSIONAL OBJECTIVE To work in research and
development as an R&D Engineer, or a Consulting
Engineer . Very interested in Physics, Software
Engineering, Sales & Applications Engineering, &
Instructional Activities.

SUMMARY An Engineer with extensive experience in
HEWLETT-PACKARD (PC & Servers Divisions), APPLE
COMPUTER, and LOCKHEED-MARTIN. Strong analytical and
mathematical capabilities, with effective application
of EM theory to design and testing. An R&D
Engineering Scientist who maintains friendly
relationships by listening to other perspectives.

TECHNICAL SUMMARY
January 2000 to date: Consulting Engineering and
Investments in Start-Up Companies (BitMicro.com for
All Solid State hard drives).

May 1997 - December 1999: Hewlett-Packard Company,
R&D, Network Server Division and Home Products
Division, Cupertino, CA:

    EMC Engineering Lead/Senior Quality Engineering -
Hardware, Design of Devices for EMC Reduction &
    Signal Integrity Enhancement in PCBs
    * EMC Compliance Design & Testing - Domestic and
International Qualifying/ Certification of various
        products (Netservers, PCs, Monitors,
Printers, Scanners,) for all agencies - FCC, CSA,
CISPR, VCCI, ...
     * Theoretical Math/Computer Modeling & Solving
of EMC Problems by EM Theory
     * Strong Mathematical/Analytical Skills
     * Use of TDR (Time Domain Reflectometer) to
measure trace impedances, & to enhance SI
     * Use of EMC Simulation Tools -ViewLogic QUIET &
QUIET EXPERT, etc.
     * Design of Quiet Grounds for Common Mode Noise
Mitigation
     * Mechanical Design for Differential Mode Noise
Mitigation: GBS
     * Design Guidelines established for Electrical,
Electronic, and Mechanical Designs at high frequecies
     * Familiar with all current & future Intel CPUs
     * Consulting in Thermal Engineering and Fluid
Mechanical Engineering

1991-1997: Apple Computer, Inc., R&D, Macintosh
Hardware Division, Cupertino, CA:

    Staff Engineer/Senior Engineering Scientist -
Hardware, EMC Compliance Design & Testing - Domestic
and International Qualifying/Certification of various
products
     * Use of TDR measurements of trace impedances, &
to enhance Signal Integrity
     * EMC Compliance Engineering Requirement
Specifications
     * Testing & Documentation for
Certification/Verification
     * Consulting in Thermodynamics Engineering

1980-1990: Lockheed Missiles & Space Co., Inc.,
Missile Systems Division, Sunnyvale, CA:

     Lead Engineer, Project Engineer, and Research
Specialist - Hardware Production
     (a) Electronics Systems Division - electronics
survivability (immunity) analysis, nuclear radiation -
hardened systems design; EMI/RFI Test Director:
MIL-STD461 &HERO (Hazards of Electromagnetic
Radiation on Ordnance) requirements, Thermal Analysis.
     (b) Re-entry System Division - Project Engineer
for design requirements for all RF & Electrical
hardware, Thermodynamics and Flight Dynamics Analysis

20 months with Atomic Energy of Canada Ltd (nuclear
reactor development)
24 months with Australian Atomic Energy Commission
(nuclear reactor shielding)

Concurrent Academic Teaching: (Part-Time)
     * Cogswell Polytechnical College: BSEE Program
(5 Years)
     * San Jose State University: Engineering Physics
    (5 Years)

QUALIFICATIONS
    * Continuing Post-Graduate Studies at Stanford
University: electronics, electromagnetics, microwave
circuit design, computer/information/ communication
science and engineering
    * BS,MS,PhD (Engg, Math, Chem/Physics,CompSci -
Univ. of New South Wales, and Sydney, Australia)
    * 2 U.S. Patents Pending in EMC Engineering: EMI
Reduction Device, EMI Grounding Connector

PUBLICATIONS and PRESENTATIONS
   * Set of 10 volumes of Mathematics textbooks
   * Numerous papers in refereed research journals in
Fluid Dynamics, Thermodynamics, Electromagnetics
   * Paper Presented to the Santa Clara Valley Chapter
of the IEEE/EMC Society, March 14, 2000:
Effective Grounding & Shielding for GHz Processors
and Beyond

PERSONAL Citizen of U.S.A., Had Held Security
Clearance

REFERENCES Available on Request
=======================================================

--- Sean Casey <casey@td2cad.intel.com> wrote:
>
>
>
> Intel Corporation has an immediate opening for a
> signal
> integrity engineer in the Technology CAD division in
> Santa
> Clara, CA. If you are qualified and interested
> please send
> your resume to Sean Casey <sean.m.casey@intel.com>.
>
>
> Responsibilities:
>
> The opportunity is for a software developer in the
> area of
> interconnect simulation and modeling in the
> Technology CAD
> Division. The project areas deal with analysis of
> multi-level interconnect for VLSI design, including
> development and enhancement of advanced field
> solvers,
> modeling of interconnect for extraction of
> resistance,
> capacitance, and inductance from layout, and
> analysis of
> high-frequency effects. The tool and model
> development is
> critical for simulation and design of on-chip
> interconnects
> and off-chip packaging.
>
> The candidate should have a Ph.D. degree in
> electrical
> engineering, physics, or a related field with a
> strong
> background in electromagnetic field theory,
> mathematics,
> numerical analysis, and software development of
> large
> programs in C/C++. He must possess good
> communication
> skills. An understanding of semiconductor device
> theory,
> circuit theory, and experience with CAD tools is a
> plus.
>
>
>
> For more information about Intel, visit our web site
> at
> www.intel.com. Intel offers excellent compensation
> and
> benefits that include employee profit sharing, stock
> ownership plans, periodic paid sabbaticals and
> relocation
> assistance.
>
>
>
> Intel Corporation is an equal opportunity employer
> and fully
> supports affirmative action practices. Intel also
> supports a
> drug-free workplace and requires that all offers of
> employment be contingent on satisfactory
> pre-employment drug
> test results. MUST HAVE PERMANENT LEGAL RIGHT TO
> WORK IN THE
> U.S. Intel and the Intel logo are registered
> trademarks of
> Intel Corporation.
>
>
>
> **** To unsubscribe from si-list or si-list-digest:
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