From: [email protected]
Date: Mon Nov 08 1999 - 07:24:27 PST
Or try a techniques that we call "submerged traces", with the following
1. Topside components with traces just long enough to reach vias, rest of top
plane filled in with ground.
2. Signal/power/ground layer in the X-direction.
3. Signal/power/ground layer in the Y-direction.
4. Bottomside components with traces just long enough to reach vias, rest of
bottom plane filled in with ground.
For the topside and bottomside, run ground traces through ground pads/holes and
between component pads/holes anywhere you can, to make the holes/slots in the
ground plane as small as possible. If two components are side-by-side and their
pins line up perfectly (an ASIC going to a microprocessor, for example), you may
run short point-to-pointtraces just on the topside/bottomside. Otherwise all
signal routing is done in the internal layers.
The two inner layers have gridded power/ground networks, just as you would do
for a double-sided card, in addition to the signals. Since the only connections
to these layers are through plated-through holes for components and via holes
you can use minimum spacings everywhere. In addition, since these layers are
sealed off from the air you do not have to worry about creepage/clearance
requirements. I like to put a "ground ring" completely around the card on
these layers, and tie it into the topside and bottomside ground fill with vias
no further than 1/2" (12.5mm) apart. We place these vias manually, wherever we
can, and the irregular spacing helps prevent some of the resonance problems that
have been discussed on this mailing list. The overall effect is to create a
Faraday cage for the signals on the inner layers. We beef up the power and
ground traces wherever we can, and then use ground fill to get as much copper on
these inner layers as we can.
We used this technique on my last project to cram a smart 10BASE-T/100BASE-Tx
Ethernet interface onto a 4.094" x 3.740" (104mm x
95mm) 4-layer card, populated both sides, with a total of:
* 5 connectors.
* 9 IC's, including plastic quad flat packs (PQFP's) and small-outline J-lead
* 26 resistor networks.
* Over 130 passives, 0603's and up.
John Barnes Advisory
dmckean%[email protected] on 11/05/99 02:09:39 PM
Please respond to si-list%[email protected]
To: si-list%[email protected]
cc: (bcc: John Barnes/Lex/Lexmark)
Subject: Re: [SI-LIST] : Micro Noise Part 2
At 12:47 PM 11/5/99 EST, [email protected] wrote:
>I've not seen this lay-up suggested much, but it looks like it could work.
>before I go ahead and try it I thought I'd bounce the idea.....
Wild suggestion, but have you considered
GND/S1/S2/<fill>/PWR? Since it appears
to be lo-freq stuff and the fact you haven't
mentioned controlled impedence makes me
think of this stackup. Traces could then
be routed easily between S1 and S2 easily.
I've never liked working with 4 layer
boards but when you're stuck, you're stuck.
The transient testing can cause all sorts
of crazy things to occur. Proximity to the
transient without lack of good sheilding
effectiveness is one killer. At least you
could get some SE that. Doug
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