Re: [SI-LIST] : Decoupling Caps in ASIC PKG

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From: Ron Miller (rmiller@Brocade.COM)
Date: Mon Nov 01 1999 - 14:11:01 PST


Norm

I did this a couple years ago and had very good results. However, be sure
to keep the bondwires to an absolute minimum length. It can eat your lunch.

Ron Miller

"Smith, Norm W" wrote:

> Does anyone have experience in using decoupling capacitors inside an ASIC
> package?
>
> We have the option of putting up to eight 0.056uF caps - at $2.50 each -
> inside our custom ASIC package. The package is a 624pin (25 x 25 matrix)
> CBGA flip chip technology, which, of course, has no room for discrete
> decoupling caps directly underneath the package on the bottom side of the
> board. I maybe limited on placing discrete caps around the peripheral of the
> chip due to trace escape. The ASIC has approximately 220 Outputs with rise
> times of 500psec for best case conditions and 750-800psec under nominal
> conditions. Clock frequencies are 66MHz and 125MHz.
>
> Norm Smith
> NCR Corp
> San Diego
>
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--
Ronald B. Miller  _\\|//_  Signal Integrity Engineer
(408)487-8017    (' 0-0 ') fax(408)487-8017
     ==========0000-(_)0000===========
Brocade Communications Systems, 1901 Guadalupe Parkway, San Jose, CA  95131
rmiller@brocade.com,  rbmiller@sjm.infi.net

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