Re: [SI-LIST] : Decoupling Caps in ASIC PKG

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From: Pat Zabinski ([email protected])
Date: Mon Nov 01 1999 - 14:11:05 PST


At $2.50 each, these are not inexpensive add-ons.

However, I think you need to look at your system requirements. Do
you need to maintain the 500 psec edge rates? If not, then
you might be able to get by without them.

However, if you need to maintain the edge rate (or something close
to it), then I believe you'll need to put the caps in-package
in order to provide sufficient local charge storage during
logic transitions. I'm working on validating this theory, but my
initial results on one project indicate that you need to provide
enough charge storage within 1/10 risetime in order to preserve
the edge. If you have 100 farads a meter away, it doesn't do you
any good; you need the capacitance "near" the pin (where "near"
is defined as a fraction of the "resulting" edge rate).

At 66 and 125 MHz, my guess is that can (and probably should) slow
down the edge a bit. If this is the case, I'd tend to save a few
bucks and put the caps on the board.


> Does anyone have experience in using decoupling capacitors inside an ASIC
> package?
> We have the option of putting up to eight 0.056uF caps - at $2.50 each -
> inside our custom ASIC package. The package is a 624pin (25 x 25 matrix)
> CBGA flip chip technology, which, of course, has no room for discrete
> decoupling caps directly underneath the package on the bottom side of the
> board. I maybe limited on placing discrete caps around the peripheral of the
> chip due to trace escape. The ASIC has approximately 220 Outputs with rise
> times of 500psec for best case conditions and 750-800psec under nominal
> conditions. Clock frequencies are 66MHz and 125MHz.
> Norm Smith
> NCR Corp
> San Diego

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