[SI-LIST] : Decoupling Caps in ASIC PKG

From: Smith, Norm W ([email protected])
Date: Mon Nov 01 1999 - 12:49:54 PST

• Next message: [email protected]: "Re: [SI-LIST] : Comments from your SI seminar (SendII)"
• Previous message: Volk, Andrew M: "RE: [SI-LIST] : Comment on Johnson's article"
• Next in thread: Pat Zabinski: "Re: [SI-LIST] : Decoupling Caps in ASIC PKG"
• Maybe reply: Pat Zabinski: "Re: [SI-LIST] : Decoupling Caps in ASIC PKG"
• Reply: Ron Miller: "Re: [SI-LIST] : Decoupling Caps in ASIC PKG"

Does anyone have experience in using decoupling capacitors inside an ASIC
package?

We have the option of putting up to eight 0.056uF caps - at $2.50 each -
inside our custom ASIC package. The package is a 624pin (25 x 25 matrix)
CBGA flip chip technology, which, of course, has no room for discrete
decoupling caps directly underneath the package on the bottom side of the
board. I maybe limited on placing discrete caps around the peripheral of the
chip due to trace escape. The ASIC has approximately 220 Outputs with rise
times of 500psec for best case conditions and 750-800psec under nominal
conditions. Clock frequencies are 66MHz and 125MHz.

Norm Smith
NCR Corp
San Diego

**** To unsubscribe from si-list: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****

• Next message: [email protected]: "Re: [SI-LIST] : Comments from your SI seminar (SendII)"
• Previous message: Volk, Andrew M: "RE: [SI-LIST] : Comment on Johnson's article"
• Next in thread: Pat Zabinski: "Re: [SI-LIST] : Decoupling Caps in ASIC PKG"
• Maybe reply: Pat Zabinski: "Re: [SI-LIST] : Decoupling Caps in ASIC PKG"
• Reply: Ron Miller: "Re: [SI-LIST] : Decoupling Caps in ASIC PKG"

This archive was generated by hypermail 2b29 : Tue Feb 29 2000 - 11:39:29 PST