From: Larry Smith ([email protected])
Date: Mon Nov 01 1999 - 13:28:12 PST
> From: "Volk, Andrew M" <[email protected]>
>
> Larry -
>
> Very interesting simulation results. Question: I was wondering if these
> simulations took into account the 1 nH Dr. Johnson mentions as via
> inductance in connecting capacitors to the planes? Also, does the relative
> placement of these capacitors on the plane around the device have any impact
> to their interaction? How do you simulate these kind of effects?
>
> Andrew Volk
> Intel Corp.
Andrew - I used 0.7 nH for the total loop inductance of decoupling
capacitors mounted on a PCB and connected to power planes. We have
done a lot of work with this. We believe that with careful pad and
via layout and power planes close to the surface of the PCB, it is
possible to achieve 0.7 nH or even less. We have good model to
hardware correlation on this. Tanmoy Roy published a lot of this
in a paper at the 1998 EPEP conference. Some of it is repeated in
the Journal artical mentioned in the last note on this thread and in:
http://www.qsl.net/wb6tpu/si_documents/docs.html
The placement of these capacitors becomes critical above 200MHz.
We use a transmission line grid to simulate power planes. It turns
out that the power plane impedance dominates as we go above 200MHz and
below 100mOhms (rough numbers).
regards,
Larry Smith
Sun Microsystems
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