RE: [SI-LIST] : Comment on Johnson's article

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From: Larry Smith (ldsmith@lisboa.eng.sun.com)
Date: Mon Nov 01 1999 - 14:38:10 PST


> From: "Chris Cheng" <hycheng@3pardata.com>
>
> larry,
> one thing needs to be considered is the combined on die
> power distribution path and the off die package/decoupling
> power impedance path. the on die power grid and decoupling
> tends to split the plane resonance up and down. while it
> is true that plane resonance happens in the hundreds of
> megahertz range, the combined die/package/pcb power impedance
> tends to peak around 10-100MHz. this power impedance profile
> needs more low/medium frequency range capacitor in which case i
> will pick the largest possible capacitance and quantity i
> can place ie 3.3nfx5 in your example. the simplistic view of
> just looking at the pcb/decoupling cap resonance may not be
> valid for high speed design. and if you are unluck enough to
> be using wire-bond packages, the bondwire inductance will be
> so dominant that any attempt to decouple noise above 100MHz
> will be difficult if not impossible.
> chris

Chris - I agree with you concerning the inductance of the package
standing in between the PCB and the chip that is consuming the power.
The on-chip decoupling capacitance and the package inductance forms a
resonant circuit. For most of the projects that I have worked on in
the last 10 years, that resonance has been between 50 and 100 MHz. The
chip capacitance keeps going up and the package inductance keeps going
down so that the product remains fairly constant. If we are just
thinking in terms of supplying the core logic with clean power, then we
don't need to decouple the PCB much above 100 MHz. We need charge
stored on the package and/or chip to supply current above that frequency.

However, a peak in the PCB power distribution impedance above 100 MHz
can hurt us badly in terms of EMI. Sure, the package makes a nice low
pass filter that tends to contain chip noise. But suppose we have 20
dB of isolation from the chip to the PCB at 500 MHz. If we are
consuming 50 watts of power at 500MHz (very possible with modern uP)
then 5 watts make it to the PCB. We certainly do not want peaks in the
power distribution system impedance that can be stimulated to resonance
by some clock or harmonic.

Also, the IO circuits depend upon the power planes to carry return
current. Under some conditions, that return current must pass between
the Vdd and Gnd power planes. With sub nSec rise times, we need low
impedance between the Vdd and Gnd PCB power planes up to nearly 1 GHz.
This is accomplished by discrete capacitors working together with
power plane pairs (VDD and Gnd).

regards,
Larry Smith
Sun Microsystems

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