RE: [SI-LIST] : Comment on Johnson's article

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From: Chris Cheng (hycheng@3pardata.com)
Date: Mon Nov 01 1999 - 13:42:11 PST


larry,
   one thing needs to be considered is the combined on die
power distribution path and the off die package/decoupling
power impedance path. the on die power grid and decoupling
tends to split the plane resonance up and down. while it
is true that plane resonance happens in the hundreds of
megahertz range, the combined die/package/pcb power impedance
tends to peak around 10-100MHz. this power impedance profile
needs more low/medium frequency range capacitor in which case i
will pick the largest possible capacitance and quantity i
can place ie 3.3nfx5 in your example. the simplistic view of
just looking at the pcb/decoupling cap resonance may not be
valid for high speed design. and if you are unluck enough to
be using wire-bond packages, the bondwire inductance will be
so dominant that any attempt to decouple noise above 100MHz
will be difficult if not impossible.
chris

> -----Original Message-----
> From: owner-si-list@silab.eng.sun.com
> [mailto:owner-si-list@silab.eng.sun.com]On Behalf Of Larry Smith
> Sent: Monday, November 01, 1999 11:53 AM
> To: si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : Comment on Johnson's article
>
>
> Arrigo - It is true that inductance is an extremely important parameter
> for decoupling capacitors and a low inductive impedance between the
> power rails is useful in reducing noise.
>
> But to get a complete picture, we need to consider the L, C and R of
> the decoupling capacitors. A good model for ceramic decoupling
> capacitors is a series RLC circuit. If we had perfect (lossless) L and
> C, the decoupling capacitor would be zero impedance(!) at the series
> resonant frequency which is 1/sqrt(LC). But, all capacitors have loss
> which is usually represented as equivalent series resistance, ESR. For
> many ceramic decoupling capacitors, the ESR is a lower impedance than
> jwL or 1/jwc, leading to nice minimum impedance at resonant frequency.
> A gif file is attached that shows frequency domain spice analysis of a
> small menu of individual 0805 size decoupling capacitors:
>
>
> 3.3nF 0.7nH 142mOhms
> 2.2nF 0.7nH 155mOhms
> 1.5nF 0.7nH 168mOhms
> 1.0nF 0.7nH 158mOhms
>
> Suppose we have a system that requires a power supply with an impedance
> of 100 mOhms between 100 and 200 MHz. We have room for just 5
> capacitors that are 0805 size. What are the best 5 capacitors that we
> can choose?
>
> None of the capacitors on the menu have 100 mOhms of impedance, but if
> we parallel them up we can get less than 100 mOhms of impedance.
> First, try using 5x3.3nF. The spice analysis in the lower panel of the
> .gif file shows that at 100 MHz, we are far below 100 mOhms, but do
> not meet requirements at 200 MHz.
>
> We might try using 2x3.3nF in parallel with 3x1.0 nF. This combination
> works well at 100MHz and 200MHz, but leaves a bad 'anti-resonance' at
> 150MHz. The anti resonance occurs when one capacitor has gone
> inductive and another capacitor is still capacitive. It forms a
> parallel RLC circuit that has a dangerous high impedance at some
> frequency.
>
> The best choice is to use one of each of the above capacitors and double
> up on the 1nF, for a total of 5 capacitors. The five capacitors in
> parallel make a nice flat impedance between 100MHz and 200MHz. The ESR
> for lower value capacitors tends to be higher because fewer plates are
> used in the construction.
>
> A word of warning: Power planes have very high quality (low inductance,
> low ESR) capacitance. Four mil thick FR4 has a capacitance of 225 pF
> per square inch. If we use discrete capacitors to decouple a set of
> FR4 power planes, there will be a large antiresonance at some higher
> frequency. The lower panel shows the antiresonance at about 500 MHz
> when 4 square inches of power plane are decoupled with 5x3.3nF. The
> high Q circuit formed by low ESR capacitors attached to power planes
> through inductive vias/pads can result in EMI problems.
>
> Several of us at Sun have published a paper in the IEEE Transactions on
> Advance Packaging, Aug 1999, Vol 22, Number 3. The paper gives much
> more details on power distribution and decoupling capacitors. A soft
> copy is available at:
>
        http://www.qsl.net/wb6tpu/si_documents/docs.html

regards,
Larry Smith
Sun Microsystems

> Date: Sun, 31 Oct 1999 23:56:05 -0800
>
> Dear SI experts,
>
> I have a question on the article posted on Dr. Johnson's web site at
>
> http://www.sigcon.com/news/2_3.htm
>
> entitled `Bypass Capacitor Layout'. At the end of the article
> Dr. Johnson's states that since the only parameter that affects the
> performance of bypass capacitors at high frequency is their parasitic
> inductance, there is no point in using many small capacitors, rather
> the highest value capacitor in the chosen package should be used.
>
> Isn't this in contraddiction with the principle, also stated in the
> book, that many small capacitors are a better choice since the total
> parasitic inductance is lower? After the series resonant frequency
> of 1/sqrt(LC) the impedance goes up with 20 dB/decade slope so the
> only way to decrease it is by lowering either L or C, so both L and C
> are important.
>
> Am I missing something?
>
> Thanks in advance,
>
> -Arrigo

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