Re: [SI-LIST] : On chip decoupling

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From: Lynne Green (lgreen@cadence.com)
Date: Fri May 25 2001 - 17:33:20 PDT


Wherever power/ground run in "parallel", (over the IO or
in the core), you can use whatever layers are not used
for routing for caps (such as M2=P,M3=G,M4=P,M5=G).
Interleaved metal can provide a lot of capacitance when
the oxides are thin.

Some designers put similar structures in the core region
(on P1/P2/M1/M2) where empty space occurs (unused
cell space).

- Lynne

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