From: Zabinski, Patrick J. ([email protected])
Date: Mon Mar 19 2001 - 10:33:56 PST
Based simply on testing actual devices, we have seen the
plating bar stubs (tails) at 35 psec edge rates present
a capacitive blip up to 300 mrho (30%). Taking a guess
that the edge rates you're considering for 500 MHz are
around 200 psec, an extrapolation would put an expected
reflection at about 40-60 mrho (4-6%).
I do not know what effective capacitance the stubs present,
but they provide little in terms of impedance mismatch.
Note: Our tests were done on plastic ball grid array packages
with a good signal return path (solid plane), roughly 50 ohm
lines (microstrip), and tails less than 6 mm (250 mils)
in length. Other sizes/processes/etc are likely to
Hope this helps,
> In a PBGA substrate there are plating tails that project from
> the last via to ball connection to the edge of the substrate.
> Since there is no current flowing through these traces,
> inductance shouldn't be a problem at any frequency. Are
> there capacitive
> issues at high frequencies, say above 500mHz?
**** To unsubscribe from si-list or si-list-digest: send e-mail to
[email protected] In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Thu Jun 21 2001 - 10:11:15 PDT