[SI-LIST] : Plating Tails at High Frequencies

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From: [email protected]
Date: Mon Mar 19 2001 - 10:07:57 PST

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Reply: Scott McMorrow: "Re: [SI-LIST] : Plating Tails at High Frequencies"

In a PBGA substrate there are plating tails that project from the last via to ball connection to the edge of the substrate. Since there is no current flowing through these traces, inductance shouldn't be a problem at any frequency. Are there capacitive
issues at high frequencies, say above 500mHz?

Thanks,

--Wayne
-------------------------------------------------------------------------------------------------------------
Philips Semiconductors - ATO Innovation San Jose
Wayne A. Nunn
Staff Engineer

1101 McKay Drive
San Jose, Ca 95131 < Voice: 408.474.5620 Fax: 408.474.5505 >
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Next message: Zabinski, Patrick J.: "RE: [SI-LIST] : Plating Tails at High Frequencies"
Previous message: Larry Smith: "RE: [SI-LIST] : Layout of Bypass Cap"
Next in thread: Zabinski, Patrick J.: "RE: [SI-LIST] : Plating Tails at High Frequencies"
Maybe reply: Zabinski, Patrick J.: "RE: [SI-LIST] : Plating Tails at High Frequencies"
Maybe reply: Ozgur Misman: "Re: [SI-LIST] : Plating Tails at High Frequencies"
Maybe reply: [email protected]: "Re: [SI-LIST] : Plating Tails at High Frequencies"
Reply: Scott McMorrow: "Re: [SI-LIST] : Plating Tails at High Frequencies"

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