Re: [SI-LIST] : Plating Tails at High Frequencies

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From: Ozgur Misman (omism@amkor.com)
Date: Mon Mar 19 2001 - 10:54:50 PST


Hi Wayne,

Package stubs are plating tails introduced by the manufacturing requirements.
Stubs are required if your traces are electroplated copper. There are also
processes that do not require electroplating such as full body gold in which
case you won't have the stubs.

Having said that, how the stubs behave is a function of their electrical length.
If your stubs are electrically short they could be considered as a lumped
capacitive load. A rule of thumb is TDstub<1/2Trise (from high speed digital
design .A handbook of Interconnect Theory and design practises). If they are
electrically long , TDstub>1/2Trise you should model them as a transmission
line. The effect is , as you would expect rise time degradation, additional
delay and ringing primarily.
If you have high speed signal in PBGA type of package. I would use a 4 layer
PBGA featuring internal power and ground planes. Then route the high speed
signals (if you can) such that their respective wirebond lengths and trace
parasitics are minimum. That, essentially translates to pins closer to the
middle of the package.
I typically recommend the middle of the package, outer rows for high speed
signals!. Outer rows has much shorter stubs. Also insert G or P pins among HS
signal for better isolation.

Hope this helps!
Ozgur
Sr. Engineer/Scientist
Amkor Technology

wayne.nunn@philips.com on 03/19/2001 11:07:57 AM

Please respond to wayne.nunn@philips.com
                                                              
                                                              
                                                              
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 Subject: [SI-LIST] : Plating Tails at High Frequencies
                                                              

In a PBGA substrate there are plating tails that project from the last via to
ball connection to the edge of the substrate. Since there is no current flowing
through these traces, inductance shouldn't be a problem at any frequency. Are
there capacitive
issues at high frequencies, say above 500mHz?

Thanks,

--Wayne
-------------------------------------------------------------------------------------------------------------

Philips Semiconductors - ATO Innovation San Jose
Wayne A. Nunn
Staff Engineer

1101 McKay Drive
San Jose, Ca 95131 < Voice: 408.474.5620 Fax: 408.474.5505
>
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