RE: [SI-LIST] : Simulation of address and data bus

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From: Greim, Michael (mgreim@sonusnet.com)
Date: Thu Mar 08 2001 - 10:49:04 PST


Yes, you can use a piecewise linear source to create a
psuedo random sequence to drive your simulations within
hspice. I have seen scripts to auto magically create this
for you.

Best Regards,

Michael C. Greim Sonus Networks
mgreim@sonusnet.com 978-589-8336

Making the world safe for digital signals everywhere

And all this science I don't understand
It's just my job six days a week

The time is gone. The email's over
Thought I'd something more to say......

-----Original Message-----
From: Jim Freeman [mailto:freeman@broadcom.com]
Sent: Thursday, March 08, 2001 1:31 PM
To: Mike LaBonte
Cc: Patel, Bhavesh; si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : Simulation of address and data bus

I do this using Hspice

Jim Freeman

Mike LaBonte wrote:

> Bhavesh,
>
> I would recommend running logic patterns for data and address, even if
> you do it for only one signal at a time. As long as there is enough
> charge storage on the net to make a measurable difference one edge later,
> the possibility of pattern dependent ISI should be investigated. I
> don't think you can run your data at any regular frequency and rest
> assured that all bases are covered.
>
> There are SI tools that will apply random patterns or patterns that you
> determine.
>
> Mike LaBonte
>
> "Patel, Bhavesh" wrote:
> >
> > Hi! I had a question regarding simulations of address and data bus at
> > particular frequencies. Say, if the chip is being clocked at 166Mhz do
we do
> > simulations of the address and data bus to the chip at 166Mhz or do we
do it
> > at half the clock frequency.? What would give an approx real world
scenario,
> > simulation at the clock frequency or half the clock frequency?
> >
> > Thanks
> > Bhavesh
> >
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