From: S. Weir ([email protected])
Date: Sat Mar 03 2001 - 14:06:55 PST
I think the risk here is DC imbalance building up too quickly. In order
for a very small cap to work, the code pattern has to be balanced well
above the pole. @ 50pF / 50 ohms this is only 2.5nS. Even @ OC-192 rates
this is not going to be enough. The imbalance will be the result of any
integrated asymmetry in the wave forms of the individual drivers. This
only nulls-out when we integrate across a period where the code sequence is
DC balanced. For most codes out there, a fairly low frequency pole is
needed to avoid jitter from the symbol pattern.
At 12:51 PM 3/3/01 -0800, you wrote:
>You make a good point. I like the idea of termination of only the high
>signals without providing a path for the lower frequency garbage from inverter
> power supplys and such.
>Thanks for the suggestion.
>>From: [email protected] [mailto:[email protected]]
>>Sent: Saturday, March 03, 2001 12:41 PM
>>To: [email protected]; [email protected];
>>[email protected]; [email protected]
>>Subject: Re: [SI-LIST] : Combined single-ended/differential termination
>>Ron, I believe I've read that common mode noise on the input of PECL devices
>>(and maybe some others) can produce jitter on the output. I've also noted
>>that when people call out a capacitor for providing a common mode
>>(when the differential termination is two seriesed 50 ohm resistors,
>>capacitor to ground at the center tap) the value is usually .01ufd. It
>>like the high frequency components are the primary offenders, due to reduced
>>common mode rejection of the input stage of the receiver, as well as
>>unbalances in the two sides of the driver. I believe it would be a
>>reasonable compromise to use a 30-70pf capacitor in order to provide common
>>mode termination just at the higher end of the spectrum. What do you think?
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