Under construction




Universal GPS Disciplined Oscillator (GPSDO) using ADF4001 PLL governed by 10KHz GPS reference. It can be configurated to discipline various frequencies between 5...200MHz, 10KHz step "channel".

Disciplined oscillator must to have good short time stability, otherwise the PLL will be unable to lock. Oven controlled oscillator (OCXO) is recommended. Output tuning voltage is 0...+5V. ADF4001 PLL register values are stored inside of ATMEGA328 uC. Four (4) preprogramed frequencies can be selected by jumpers according OCXO frequency: 5MHz / 10MHz / 13MHz / 20MHz. Software modifications are required for others frequencies.

Navman TU60 GPS RX was chose due to 10KHz output. 1pps GPS receivers are not suitable for this project. Check my version of VE2ZAZ 1pps GPSDO. The short time stability of 10KHz is not perfect but it will be integrated through OCXO and loop filter. Long term stability of OCXO is improved by GPS. In this way excellent global stability has achieved.

ATMEGA328 provide also the serial configuration for GPS receiver. Serial communication speed is 9600 baud, values are sent after 1.5 sec from power up.

TU60 GPS receiver configuration for GPSDO application:
- Enable "@@Ea" position/status message;
- Position Hold mode;
- Satellite Mask angle 10 degrees;
- Enable 1pps output if TRAIM Alarm is OK (less than 800nsec);
- Checksums for above commands;

TU60's 1pps output and @@Ea status message are analyzed for 3D fix detection.
GPS status can be monitored via serial connection between TU60 and PC. USB/UART interface is required (FT232, CH340, PL2303...) or MAX232 for native RS232 COM port.
TU60 Motorola binary protocol is supported by Tac32 or WinOncore software.

PLL Lock detection is fairly tricky due to 10KHz small phase error which must to be detected. ADF4001 internal Digital Lock Detector (DLD) is not suitable for VCXO applications. After experiments confirmed by Application Note AN-873, Analog Lock Detection (ALD) was used. Narrow pulses provided on MUXOUT ALD pin are filtered by RC circuit and then compared by uC. When lock detection voltage is higher than 4.55V, Lock detection LED is activated. For the moment voltage setpoint is fixed but next software version will be designed to support adjustable LOCK detection setpoint.

ADF4001 registers calculated using AD Int-N PLL Software:

Reference = 10KHz
Charge pump current = 2.5mA
Muxout = Analog Lock Detect
Initialization Latch: 0D8086
Function Latch: 0D80D2
R: 100004
N: 01F401
R: 100004
N: 03E801
R: 100004
N: 051401
R: 100004
N: 07D001

Schematic GPSDO ADF4001 rev.2
Firmware vers.1 - 5, 10, 13, 20MHz
Analog Device AN-873




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