**From:** Prasad Venugopal (*[email protected]*)

**Date:** Mon Feb 26 2001 - 07:16:49 PST

**Next message:**Steve Rogers: "[SI-LIST] : chip inductor Q as a function of orientation (Thanks to all invol ved for input)"**Previous message:**selvaraj subramanian : "[SI-LIST] : Termination scheme for SSTL2 Class II"**Maybe in reply to:**Stockalis, Anthony: "[SI-LIST] : Differential End Termination"

Hi,

I would like to bring-up a few points also about the two termination schemes and add to the question from Anthony.

- two 50 ohms with the .01 uF capacitor to GND at the junction of the two 50 ohm resistors, is to terminate any common mode signal that arises as a result of driver mismatch or transmission line diff-pair mismatch. usually the mismatch is of a very short duration, which means high frequency. is that correct? if so, then we are relying on the capacitor being a short at the mismatch frequencies. is this a good assumption? if the driver is well balanced and the two legs of the transmission line are well balanced then there would be no need for the .01 uF cap. correct?

- if we want to terminate both the common-mode mismatch and the diff pair correctly, isn't it better to terminate each line of the diff-pair in 50 ohms separately to ground?

- i understand if the receiver does not like a 50 ohm dc path to ground, then there is no choice of putting the 50 ohms to ground - which then makes the original question more important i.e is a 100 ohm across better?

- 0.01uF capacitors have a resonant frequency. If we can calculate the frequency range of the broadband signals carried by the transmission line, 125 MHz to 625 x 5 MHz => 3 GHz, in the case of gigabit ethernet( fundamental of 101010 at 1.25Gb/s = 625 MHz x 5th harmonic) where should the resonant frequency notch be placed? of course this would affect the impedance of the transmission line, in which case where should the cap physically be placed? My guess is at the transmitter, within say 1/4 the wavelength of 3GHz => 25 mm away. correct? is x7r a good choice - any experience good or bad with the same?

Thanks,

Prasad

-----Original Message-----

From: Stockalis, Anthony [mailto:[email protected]]

Sent: Friday, February 23, 2001 2:36 PM

To: '[email protected]'

Subject: RE: [SI-LIST] : Differential End Termination

The suggested termination scheme is a .01uF series capacitor on each line

into the load along with a 50ohm .01uF AC terminator to gnd. The other

termination scheme is to have .01uF series capacitors into the load and a

100ohm resistor between the two pairs to match with the 50 ohm impedence of

the trace. I have contacted the manufacturer, but I am waiting to get a

response. I wanted to see if anyone had tried using either of these

termination schemes.

Thanks,

Anthony Stockalis

Marconi Communications

BXR-48000 Hardware Team

email: [email protected]

Phone 724-742-6124

-----Original Message-----

From: Fred Balistreri [mailto:[email protected]]

Sent: Friday, February 23, 2001 4:12 PM

To: Stockalis, Anthony

Subject: Re: [SI-LIST] : Differential End Termination

Hello Anthony, the two resistors with a common capacitor method will

work. However I would get better clarification with what the IC chip

manufacturer told you. The 50 ohms with a .01uf capacitor acting as AC load

will not

work. The .01uf they are talking about may be in series with the driving

device to block any DC currents. This is common on some Transeiver chips

which

don't like DC currents on the input. In this case the terminating resistor

is

across the differential and should be choosen for the differential impedance

of the

connecting transmission lines not necessarily 50 ohms. I don't believe that

the IC

manufacturer would make such a mistake. The problem may be in communication.

Get a

sketch/schematic of what they are saying for clarification.

Best Regards,

"Stockalis, Anthony" wrote:

*>
*

*> I am investigating the ac end termination of a differential data signal.
*

I

*> have reviewed section 6.4 of Howard Johnson's "Handbook of Black Magic" on
*

*> ac end terminators, and it seems that two resistors to a common capacitor
*

to

*> ground is the way to go. The recommendation of the chip manufacturer is
*

to

*> have a 50 ohm to .01uF capactor end termination on each line of the
*

*> differential pair. The chip is a Gigabit Ethernet Chip running at
*

1.25Ghz.

*> This capacitance value seems rather high to me, and I believe that the
*

*> common capacitor would be the correct solution. I was wondering if anyone
*

*> else has any valuable experience doing ac end terminations on differential
*

*> data lines. I have used the Mentor Graphics Interconnectix simulator, but
*

*> have not gotten very conclusive results because a random data signal
*

cannot

*> be used in the tool. Any help would be appreciated.
*

*>
*

*> Thanks,
*

*>
*

*> Anthony Stockalis
*

*> Marconi Communications
*

*> BXR-48000 Hardware Team
*

*> email: [email protected]
*

*> Phone 724-742-6124
*

*>
*

*> **** To unsubscribe from si-list or si-list-digest: send e-mail to
*

*> [email protected] In the BODY of message put: UNSUBSCRIBE
*

*> si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
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*> si-list archives are accessible at http://www.qsl.net/wb6tpu
*

*> ****
*

-- Fred Balistreri [email protected]**** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected] In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu ****

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**Next message:**Steve Rogers: "[SI-LIST] : chip inductor Q as a function of orientation (Thanks to all invol ved for input)"**Previous message:**selvaraj subramanian : "[SI-LIST] : Termination scheme for SSTL2 Class II"**Maybe in reply to:**Stockalis, Anthony: "[SI-LIST] : Differential End Termination"

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