From: Michael Nudelman ([email protected])
Date: Fri Nov 03 2000 - 06:09:14 PST
Q1. Is there not a TTL/CMOS low jitter generator, so you don't have to
go through translation? I remember very low jitter clocks from
PLETRONICS/SARONIX, with also high rise time (guaranteed sub-nanosec)
(i.e. QLogic chips required such clocks and I bought them from
Pletronics).
Q2. Have you looked at the power right at the VCC of your
clock/translator/buffer, if there is any noise there during the CPU
being active.
Q3. I have my PECL/CML clocks decoupled through LC filter in the VCC.
Honestly, I never checked how effective it is - siffices it to say, that
the filter is not taking much space and the device works fine.
Q4. Have you terminated for the common mode or just for single-pole
mode? If you have cross-talk, your diffpair will pick up some common
mode noise, and unterminated for common mode it will add to the jitter.
Mike.
ARTHUR BROWN wrote:
> Hello SI experts,
>
> I have a 12 layer board. The board has 2 power
> planes, 4 ground plane and 6 signal planes.
>
> This is a digital board with processor, memory,
> glue logic, framers, packet processors etc.
>
> The framer requires very low jitter clock.
> This clock is coming into the card at
> 77.76 Mhz PECL differential. The clock is
> first buffered using a PECL buffer. Then
> clock is translated using PECL to TTL
> translator and given to the framer.
>
> Now my problem.
>
> When there is no activity on the card there
> is a certain value of jitter on the clock
> at the framer. Now I generate activity on
> the board - processor does continuous
> memory accesses and enable packet transfer
> processing/framing etc. at full rate.
> Then the jitter on the clock at the framer
> is considerably higher.
>
> Now my question
>
> Will I attribute the above observation to
> noise on the Ref planes due to return
> current paths.
> I think not because the TTL clock is
> routed through an inner stripline layer
> and separated from all other traces by
> 150 mil on either side for all traces
> between the ref planes of this stripline
> layer. Does anyone think otherwise.
>
> Or
>
> Will I attribute it to improper power
> plane decoupling.
>
> If so then how do I analyse for
> power plane resonance due to capacitor
> lead, via, pad inductance for the few
> hundred decoupling capacitors I have
> on the board. Are there any tools which
> does this.
>
> Any help, insight, suggestions will
> be highly appreciated.
>
> Regards,
>
>
>
> =====
> Arthur Brown
> HSSI Consulting,
> 16 Ang Mo Kio Street 80 - Level 4
> Ang Mo Kio Industrial Park 4,
> Singapore-569088
> Tel:(65)489 9999
> email: [email protected]
>
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