From: Ray Anderson ([email protected])
Date: Fri Jan 28 2000 - 10:41:14 PST
Issac Cheng <[email protected]> wrote:
> Raymond Anderson,
> I've read your paper on Power Distribution System Design Methodology and
> Capacitor selection for Modern CMOS technology. I found it excellent and
> well written. I hv some questions here regarding to the topic.
> 1. From figure 12(showing the anti-resonance of parallel caps), how do you
> add up two Z-Freq response graphs to get the anti-resonance?
> 2. Say I got the R and X values of a cap for various freq(100, 1K, 10K,
> 100K, 1MHz), say, how can I plot out the Z vs Freq graph for 2 caps(same
> question as above, but it's actually asking how to calculate it and put it
> on a graph)?
> 3. For the formula in estimating the needed decoupling capacitance for a
> PDS, ie. C=I(dt/dv), how do you estimate I and dt here? I is the transient
> current, is it the Imax in the system? dt is the VRM respond time, how do
> you get dt? Is it from the VRM spec or somewhere else?
> 4. Do you do a 'anti-resonance' and Ztarget check at then end of your
> simulation for PDS?
> Isaac Chang
Issac, thank you for your kind comments on our paper. The lion's share of the
compliments should go to my colleague Larry Smith who was primarily responsible
for spearheading our group's work that led to the paper.
As Istvan has pointed out (3 time zones ahead of me), the anti-resonances
plotted in Figure 12 are numerically the result of a parallel combination of
the impedances of the two series RLC circuits. This can be calculated by summing
the admittances of the circuits and then taking the reciprocal of the result
(parallel impedances are similar to parallel resistances, EE101 stuff). The
actual plots included in the paper are a result of a simple Hspice
simulation. The same plots could have been produced with numerical
calculations in Matlab, in a spreadsheet, or by hand as Istvan pointed out.
If you have tabulated R and X values I guess you could curve fit those values to
and expression of Z for each RLC ckt. and then parallel the combination as described
above. You could even do it in spice if you figure out how to represent a ckt as
a table of values.
The current we are interested in is the delta current. Suppose you have a system
that draws 40 amps DC. You also know that its current consumption varies between
40 amps maximum when it is running at full speed and executing code, and it draws
30 amps when idling in the sleep mode. It is the 10 amp delta (40-30) or transient
current that you are interested in. The dt value is determined by the dynamic response
of the VRM (which is determined by the loop response of the VRM). The dt number can be
estimated by looking at a plot of the transient current response of the VRM and noting
how long it takes the supply to ramp the transient current up or down. It can be
extracted from the spec, measurement, or simulation (if you have enough time...).
After a simulation run, the resulting Z profile is compared to the target impedance
determined for the system. The goal is to produce a decoupling solution that lies
below the target-Z. Anti-resonances, if not managed can exceed the target Z and may
be problematic in that they represent high impedances at specific frequencies that may
cause system malfunctions if the system needs to draw appreciable current at those frequencies
and also may spell bad news for EMI radiation at those frequencies as well. It is the
job of the designer to manage the number, value and position of the decaps to produce
a broadband, flat, low impedance response profile that keeps below the calculated target-z.
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