If I may ask - what are you doing with the signals that you usually
"don't neglect."
Are you using any SI tools and a process for design, analysis and
verifcation of
those nets?
If the existing process doesn't cover the needs for your 'house
keeping' nets then you're company is now faced with having to buy and
support yet
another tool to complete the job. If nothing much is being done on
that front either then I suggest spending the money and get the tools
that can cover all
your company's needs. My recommendation would be to
spend the money and get XTK.
Here is the one feature that addresses your particular needs for which
you cannot find comparable capability and performance in any other tool.
The Batch capabilty - all your design's nets get crunched at one time -
great feature for
your predicament. Its a perfect way to cover those "neglected nets".
What more
there's not much work on youpart if someone else is running the tools to
cover those
so called "critical" nets. This feature is one of XTK's traditional
strong points and
only practical and feasible due to the analysis performance of the
underlying engine.
Working with Allegro board files is also very easy. There is essential
one control file that
control all aspects of the translation. Its capabiltity allows for the
analysis of multiboard
systems, each of which can be from a different layout system. Allegro,
Mentor, PADS, PCAD,
CCT and others. When analyzing multboard
systems one often analyzes configurations consisting of legacy card
designs - as with any of the
supported backend systems there's no need to "uprev" your design
databases to analyze them
in XTK.
What is also important to note is that the layout need not be completely
placed or routed so
you don't need to wait until the board is done to get the warm and
fuzzies. Anything
that is routed will be analyzed using the actual etch data and all
ratsnets will be analyzed
using the manhattan distances and will reflect the currently imposed net
scheduling if any.
XTK is available from Viewlogic. Check their web site
(www.viewlogic.com) for contact info.
Marc
> -----Original Message-----
> From: Ron Miller [SMTP:[email protected]]
> Sent: Thursday, September 02, 1999 1:18 PM
> To: [email protected]
> Subject: [SI-LIST] : Automatic/Semi-automatic design check of PCB
> layout database for crosstalk/SI violations.
>
> Hi Guys
>
> What technique or tools are being used for checking a new PCB layout
> database for simple
> mistakes, like excess crosstalk or "BIG" impedance mismatches before
> releasing a PCB
> for FAB.
>
> My focus is the housekeeping signals and lower speed busses, that we
> usually neglect but which
> can still bite us in the posterior, causing a new spin of artwork and
> FAB.
>
> Requirements in order of importance:
> 1. Compatibility with PCB databases like Allegro/Cadence
> 2. Simple to use, little or no training
> 3. Cost of acquiring
> 4. Speed of processing
>
> If there is not such a product someone needs to get busy.
>
> Ron Miller
>
>
>
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