HR_C5000 datasheet


This document is based on a datasheet for the HR_C5000 written in Chinese.
Fragments were copied and pasted into Google Translate, and the english translation was copied from here.
When finished and double-checked, fragments from this file may eventually find their way to the MD380 Tool's C5000 baseband chip documentation.
Last modified: 2016-12-27 (DL4YHF).
The original datsheet was downloaded from
This document, along with all embedded images, can be downloaded from
Blocks marked like this were added later, with comments and references to the MD380 tools.


Device Characteristics

  1. high-performance 4FSK modulation and demodulation
  2. ETSI-compliant DMR Tire Tier I / II protocol designed to support the physical layer,
    data link layer and call control layer Independent application
  3. The use of TDMA technology to support full-duplex, half-duplex voice, data communications,
    support for relay mode applications
  4. Built-in high-performance 10bit AD / DA
  5. support FM modulation and demodulation
  6. to support analog voice compression, decompression, pre-emphasis, to increase
  7. Support baseband IQ, variable frequency IQ, variable frequency and two-point modulation and other RF interfaces
  8. Support time-sharing RF channel control
  9. Built-in high-performance CodeC, support differential Mic input and Line output
  10. Support external CodeC I 2 S interface
  11. Supports the SPI and C-BUS interfaces of the CMX638
  12. Supports AMBE3000's SPI and McBSP interfaces
  13. Supports SPI user data interface for digital voice recording, playback and beep input
  14. LQFP or VQFN two packages to choose from
  15. low power consumption management, core 1.2V, IO 3.3V


  1. Public digital interphone
  2. encrypted digital mobile radio
  3. military man digital radio
  4. Digital trunked terminals
  5. Wireless ring
  6. wireless sensor network
  7. wireless alarm system
  8. Greatly modified DMR amateur radio handheld transceivers :o)

Figure 1

Technical Data


HR_C5000 is Hong Rui independent research and development in line with ETSI TS102 361 (DMR) standard digital intercom dedicated chip. Chip using 4FSK modulation and demodulation technology, 12.5K channel using 2-slot TDMA communication mechanism to achieve 2 Way digital voice and data communication transmission, support full-duplex, half-duplex communication.
Chip design uses the physical layer, data link layer and call control layer layered design, independent open user interface, fully open Put the state information and configure the interface, user-depth development of the second to support the agreement parameter configuration, suitable for digital intercom Handsets, private cluster terminals and low-speed data, voice transmission terminal applications, support for trunk and end-to-end use.
Chip using C-Bus and McBSP interface seamless docking CMX638, AMBE3000 other vocoder chip, while mentioning For standard SPI interface, flexible selection of vocoder, support for encrypted voice, data interface, while digital voice recording, playback And a tone input providing interface.
Built-in CodeC, Mic input and Line output, providing Mic gain control and LineOut volume control, there are Effectively reduces user peripherals and configures standard I 2 S interfaces for external CodeC.
Chip built-in high-performance dual-channel AD / DA unit to support baseband IQ, can be configured IF IQ, can be configured IF and two Point modulation and other RF interfaces to provide independent IQ bias voltage adjustable design, IQ Road, you can set the cepstrum. Using standard analog walkie-talkie processing unit to support 12.5KHz / 25KHz channel communication.
3.3V power supply chip, built-in power management module, to achieve low-power design.
The product is available in 80-pin LQFP or VQFN packages.

    Indeed, there's even a REGISTER for the microphone gain - see table 2.

Block diagram

Pin definitions / Table 1 on pages 3 to 5:
1HPVCCAIHP power supply 3.3 V
2HPOUTAOHP output (n.c. in MD380)
5MIC2_NAIMic2 input N
6MIC2_PAIMic2 input P
7MIC1_NAIMic1 input N
8MIC1_PAIMic1 input P
9CDC_AVCCAICodec analog power supply, 3.3 V
10LINEOUTAOLine out (MD380: via PA to speaker)
11MICBIASAOMic bias voltage (MD380: just a C to GND?)
12, voltages and GND
14XTALDIClock input (MD380: 29.4912 MHz, X201)
15CKOutDOClock output (MD380: n.c.(?) )
16MCLKDICodeC clock input (MD380: n.c.(?) )
21McBSP_RxDDOAMBE3000 Interface (CMX638: C_CDATA)
22McBSP_TxDDIAMBE3000 Interface
23McBSP_CLKRDOAMBE3000 Interface
24McBSP_FSXDIAMBE3000 Interface
25McBSP_CLKXDIAMBE3000 Interface
26McBSP_FSRDOAMBE3000 Interface
27PKT_RX_WAKEDOAMBE3000 Interface
28RTSDIAMBE3000 Interface
29TX_RQSTDOAMBE3000 Interface
30TX_RDYDIAMBE3000 Interface
41C_CSDOCodeC interface with vocoder SPI2
42C_SCLKDOCodeC interface with vocoder SPI2
43C_SDODOCodeC interface with vocoder SPI2
44DVSSAIDigital ground
47PWDDISleep (Power Down?)
49TIME_SLOT_INTERDO30ms interrupt
50SYS_INTERDOSystem interrupt
51RF_TX_INTERDORF transmission interrupt
52RF_RX_INTERDORF receiving terminal
53(HR-DS) / 55(MD380) ??U_SDODOUser Interface SPI0 (serial data out)
54DVDDAIDigital power supply 1.2V
55(HR-DS) / 56(MD380) ??U_SDIDIUser Interface SPI0 (serial data in)
56(HR-DS) / 58(MD380) ??U_CSDIUser Interface SPI0 (chip select in)
57(HR-DS, MD380)U_SCLKDIUser Interface SPI0 (serial clock in)
58RF_RX_ENDORF receive channel open signal
59RF_TX_ENDORF transmit channel open signal
73DAC_QVOUTAOQ-channel DAC output (IF Q-path /
baseband Q-path / IF / two points)
74DAC_AVSS33AIDAC Analog Ground
75DAC_AVDD33AIDAC power supply 3.3V
76DAC_IVOUTAOI-channel DAC output (IF I-path /
baseband I-path / IF / two points)
80DCDC_SWAODC-DC switching output
The complete list of pins is readable in the original chinese PDF.
Note the discrepancies between pin numbers in the datasheet (by HR) and the MD380 schematics !
HR_DS = pin numbers seen in the chinese HR_C5000 datasheet,
MD380 = pin numbers found in the MD380 schematics dated '2014.08.11' (??),
AI = analog in, AO = analog out, DI = digital in, DO = digital out.

In the RT3/MD380:
The text under the table says:

Peripheral references
To be measured

Address: 12 / F, Pioneer Science and Technology Building, 298 Wai Yip Road, Binjiang District, Hangzhou

Page 6 :

Chip introduction

1. Summary

HR_C5000 chip design in line with ETSI 102 361 (DMR) standards, to achieve Tier I, Tier II communication protocol, Digital voice and data communications, can be applied to digital intercom, a small central command and control system applications, dedicated cluster end End and data communication node applications.
Chip design using three separate design, the user can flexibly apply the physical layer, data link layer and call control layer, real Now different application requirements.
Chip integrated high-performance channel A / D and D / A, in the application program to achieve a variety of interface with the RF channel, packet Including baseband IQ, the user can configure the IF IQ, IF and two-point modulation signal, and the analog radio to achieve the same RF side Case integration;
integrated high-performance voice CodeC, application solutions directly to the Mic signal input, analog voice output.
To the external amplifier or headset, to reduce the user's peripheral circuit design, but also provide users with external CodeC I 2 S interface;
Chip built-in a variety of voice code interface, and CMX638, AMBE3000 achieve seamless connectivity, the chip parameters can be straight.
But also provides SPI interface for the user to use other vocoding; users can SPI interface to achieve HR_C5000 parameter configuration, data read and write and read and write state parameters,
fully open the relevant parameters of the standard.

Page 7 :

2. Parameter Configuration (~ ~ list of all registers)

Table 2

Type Address Read/
Name Default
Definition Description
Reset0x00W DMRnRst
0x00 Bit7
0 DMR protocol reset
0 Physical layer reset
0 Codec reset
0x01W/R RFTransIQMode


0x14 Bit 7
Bit 6
Bits 5..4

Bits 3..2

Bit 1
Bit 0
0 for IQ, 1 for QI
0 for IQ, 1 for QI
00 = TX intermediate frequency mode
01 = TX intermediate frequency IQ mode
10 = TX baseband IQ mode
11 = "two-point modulation mode" (?)

00 = RX intermediate frequency mode
01 = RX intermediate frequency IQ mode
10 = RX baseband IQ mode
11 : not specified in the datasheet

I/Q balancing: 1=on, 0=off (??)
0x02W/RTransIsigCenter0x00 Bits 7..0Bias value for TX, I-channel
0x03W/RRecvIsigCenter 0x00 Bits 7..0Bias value for RX, I-channel
0x04W/RTransQsigCenter0x00 Bits 7..0Bias value for TX, Q-channel
0x05W/RRecvQsigCenter0x00 Bits 7..0Bias value for RX, Q-channel
0x06W/R Vocoder-
and SPI
0x40 .. see table 12 in chapter 8
0x07W/RIFFreq20x0B Bits 7..0IF frequency, upper 8 bits
0x08W/RIFFreq10xD9 Bits 7..0IF frequency, middle 8 bits
0x09W/RIFFreq00x54 Bits 7..0IF frequency, lower 8 bits
0x0AW/RCLKOutDiv0x02 Bits 7..0External clock output freq
0x0BW/RPLLM0x0A Bits 7..0PLL M register
PLL Sleep
0x82 Bit 7
Bit 6
Bits 5..4
Bits 3..0
0=in use, 1=bypass
0=normal operation, 1=sleep
PLL output divider
PLL input divider (see note in chapter 6)
0x0DW/R Codec Ctrl
0xC8 Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bits 2..0
Codec Ctrl: details further below
Suspend: details further below
Sleep: details further below
Switch2: details further below
AntiPop: details further below
0x0EW/R HPoutEn
0x00 Bit 7
Bit 6
Bits 5..4
Bit 3
Bit 2
Bit 1
Bit 0
HP output enable 0=off,1=on
1: HP output muted
Line Out enable: 0=off, 1=on
Mic1 enable: 0=off, 1=on
Mic2 enable: 0=off, 1=on
Switch1 (?) : 0=off, 1=on
0x0F W/R ADLinVol0xB8Bits 7..3 11111: 12 dB illegal ? No modulation at all !
11110: 10.5 dB also no modulation at all !
11101: 9 dB
00000: -34.5 dB
MD380: Modifying bits 7..3 during transmit
  affects the volume of DTMF tones
  and the voice signal, depending on reg 0x0E.
  Details further below.
0x0F W/R MicVol Bits 2..1 00: 0 dB
01: 6 dB
10: 12 dB
11: 20 dB
0x10W/R ModulatorMode
0x30 Bit 7
Bit 6
Bit 5
Bits 4..3
Bit 2
Bit 1
Bit 0
0 for DMR, 1 for FM
0 for Tier1, 1 for Tier2
0 = Continue, 1 = TimeSlot
00=phys. layer, 01=?table?, 10=Layer 2
0 for non-relay, 1 for relay
0 for offset, 1 for alignment
0 indicates Slot1, 1 indicates Slot2
0x11W/R LocalChanMode0x80 Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
'Repeated'/'Direct' simplex(?)
'Repeated'/'Direct' duplex(?)
'Repeated'/'Direct' simplex with RC'(?)
'MStoFixedDuplex' (?)
'SingleFreqSimplex' (?)
'EmbeddedOutboundRC' (?)
'DedicatedOutboundRC' (?)
don't exist ?
0x14W/R LocalSrcAddrL0x01 .. ..
0x15W/R LocalSrcAddrM0x00 .. ..
0x16W/R LocalSrcAddrH0x00 .. ..
0x17W/R LocalGroupAddrL0x01 .. ..
0x18W/R LocalGroupAddrM0x00 .. ..
0x19W/R LocalGroupAddrH0x00 .. ..
0x1AW/R LocalBSAddrL0x01 .. ..
0x1BW/R LocalBSAddrM0x00 .. ..
0x1CW/R LocalBSAddrH0x00 .. ..
0x1DW/R LocalUnAddrL
0x00 .. ..
0x1EW/R LocalBroadcast
0x00 .. ..
0x1FW/R LocalEMB0x10 .. ..
0x20W/R LocalAccessPolicy0xAA .. ..
0x21W/R LocalAccessPolicy10xA0 .. ..
0x22W/R EncodeStart
0x00 Bit 7
Bit 6
Bit 5
Bit 4
Bits 3..0
1 = vocoder encoding begins
1 = end of vocoding
1 = vocoder decoding begins
1 = vocoder has finished decoding
not specified in the datasheet
0x30 W/R BCLK_CNT_H0x00Bits 7..0 Mclk / BCLK division ratio, upper 8 bit.
See Chapter 10, External Codec Clock
0x31 W/R BCLK_CNT_L0x00Bits 7..0Mclk / BCLK division ratio, lower 8 bit
0x32 W/R LRCK_CNT_H0x00Bits 7..0Mclk / LRLK division ratio, upper 8 bit
0x33 W/R LRCK_CNT_L0x00Bits 7..0Mclk / LRLK division ratio, lower 8 bit
0xF0 Bit 7
Bit 6
Bit 5
Bit 4
0 = band-pass filter off, 1 = on
0 = compression off, 1 = on
0 = pre-emphasis off, 1 = on
0 = 12.5 kHz, 1= 25 kHz
0x35W/RFM_dev_coef0xA0Bits 7..4
Bits 3..0
FM modulation factor
RSSI0x43RRSSILevelH0x00detected RSSI level, upper 8 bits
0x44RRSSILevelL0x00detected RSSI level, lower 8 bits
0x50W/RLocalDataType0x00 Bits 7..4
Bit 3
Bit 2
Bits 1..0
TX time slots DataType or A ~ F
0 = data, 1 = voice
LCSS for each transmit time slot
0x51R DLLRecvDataType
0x00 Bits 7..4
Bit 3
Bit 2
Bits 1..0
received data type
received PI
0=received data check ok, 1=error
00=no sync hdr, 01=voice,
10=data,11=table RC
0x52RDLLCC0x00 Bits 7..4
Bit 3..0
received CC (?Colour Code?)
CCL0x60W/RTransControl .. .. ..
0x61WLocalDestAddrL .. .. ..
0x62WLocalDestAddrM .. .. ..
0x63WLocalDestAddrH .. .. ..
0x64W/RLocalVoiceOACSU,... .. .. ..
0x65W/RSPEn,... .. .. ..
CCL / LC0x66W/RLocalLCPF,... .. .. ..
... ... .. .. .. .. ..
Interrupts0x82R InterRequestDeny
  Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
send request rejected
transmission is started
transmission is complete
'after the access'
received data (available?)
receiving information
'indicates exit'
physical layer receives a single interrupt
0x83W InterClear Bits 7..0 corresponding interrupt register (0x82?)
is cleared according to the bit position
0x84R SendStartVoice
  Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Voice delivery
OACSU request is sent for the first time
OACSU requests a second transmission
Vocoder config returns an interrupt
Data transmission
Partial retransmission of data
Data are all retransmitted
0x85W/R SendStartMask Bits 7..0Enable the SendStart interrupt(s?)
0x86R SendStopVoice
  Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
'The voice ends normally'
Exception: End of voice (TX timeout)
Voice OACSU waits for a timeout
The data ends normally
Data abort (transmission timeout)
Data acknowledgment timeout
0x87W/R SendStopMask Bits 7..0Enable the SendStop interrupt(s?)
0x90RRecvDataCRC Bit 7 Data fragment CRC test result.
0 = correct, 1 = CRC error.
.. .. .. .. .. The firmware seems to access other regs,
but we don't know for what purpose yet...

Bits or bitgroups which couldn't be squeezed into the above table:
Reg 0x0D, Codec Ctrl
Select whether or not to be performed by the MCU codec part of the signal control,
These Codec control signals are Suspend, Sleep, Switch2
Codec Ctrl = 1 : CPU control
Codec Ctrl = 0 : Internal Codec control module
Reg 0x0D, Codec Suspend
CodecIP whether to enter Power Down mode, active high.
1: IP enters PowerDown mode
0: IP normal operating mode
Reg 0x0D, Codec Sleep
CodecIP whether to enter the low power consumption mode.
1: IP enters low power mode
0: IP normal operating mode
Reg 0x0D, Switch2
Controls the K2 switch (?) inside the IP
1: K2 Switch on
0: K2 Switch off
Reg 0x0D, Anti-Pop
Controls whether the Codec control circuit turns on the IP burst processing,
Deactivation of Coda(?) in Codec From PowerDown / Sleep mode
Return to normal operating mode
Move(?), to avoid the "pop" sound
1: eliminate the "breaking open sound",
0: Off
Most of the register descriptions are quite readable in the chinese PDF.
The protocol to access these registers is in chapter 8, "Data read and write".
A few register values (read from an RT3 via USB) are in md380_fw.html.

Register 0x0F ("ADLinVol" + "MicVol") didn't exactly behave as listed in the orignal datasheet.
With the test setup described here, the microphone sensitivity could indeed be controlled in 1.5 dB steps, but the max 'working' value in reg 0x0F bits 7..3 was 0b11101, not 0b11111 or 0b11110. The value written by the MD380 firmware was 0b11001.

(page 15)

3. Data link layer mode

3.1 Protocol support

3.1.1. Process Control

Independent support for direct and repeater mode;
Support Aligned mode and Offset mode settings and the corresponding treatment;
ETSI TS102361-1 set up in strict accordance with the MS channel access procedures, including direct and repeater mode;
Timer parameters can be set;
Polite strategy can be set;
Hold off can be set;
Status indication;

3.1.2. Slot Framing

There are three modes for time slot framing: voice time slot packet, data time slot packet and RC packet ...
Figure 5

Supports voice slot packet super frame framing, according to
  A (SYNC), B (LC), C (LC), D (LC), E (LC), F (Null).
  Superframe combination
    Supports synchronization header selection to join;

(Page 16)
Support EMB 7bit join, carry on QR (16, 7, 6) to EMB;
Support LC 72bit join, join 5bit CS code, carry on the variable length BPTC code, interweave, join
To four time slots (128bit);
Support Null slot to join;


Figure 6


(Page 17)
Support three kinds of rate confirmed data transmission, adding 7bit SN, 9bitCRC check,
adding mask Code (different rate, different mask),
different rates of coding, interleaving, the data added 32bitCRC;

Support feedback packet data slots, add 1-2 data feedback packet,
the overall 32bitCRC check, the BPTC (196,96) encoding, interleaving;
Support last block of UDT, carry on 16bitCRC check to the data,
undertake BPTC (196, 96) Encoding, Intertwined (.... - phew !)

Figure 7

An RC signal supporting time slots RC and EMB; Support to join 7bitEMB, carry on QR (16,7,6) Encoding; Support to join the 11bit RC signal, the variable length BPTC, 32bit intertwined, added to the RC single yuan; (??)
The reception type determines the content type of the frame according to the SYNC, according to the Slot Type,
Determines the type of the received frame, and performs deinterleaving, decoding, and de-interleaving corresponding to the transmission according to the received frame type.

3.1.3. Pattern framing

Continuous mode:
Supports voice super frame framing, LC Header, PI Header or PI Header mode.
Into the super frame and join the LC Terminator;
Support data 4.8kbps framing, add data LC Header, data and LC Terminator;
Support data 9.6kbps framing, add data LC Header, data and LC Terminator.

Time slot mode:
Supports voice super frame framing, LC Header, PI Header or PI Header mode.
Into the super frame and join the LC Terminator;
Supports 4.8kbps framing of various data types, adds data LC Header, data and LC Terminator;

(Page 18)

3.2 How to use

Table 3
Slot frame typeCoding"Whether voice" (?)
Voice LC Header00000
Voice A00011
Voice B00101
Voice C00111
Voice D01001
Voice E01011
Voice F01101
Voice Terminator00100
MBC Header01000
MBC Intermediate01010
MBC Last01010
First configure the base parameters; see Table 3 DLL.

System initialization requirements in a passive state, DLL in the independent work, only to provide RF_Level signal, CPU
The establishment of the state machine, the chip has been receiving signals,
if there is synchronization information, will produce a synchronization signal trans_slot_c.
If the chip is still in sync when the send request is made, the CPU will read the RSSI value,
determine whether it can send.
If synchronization has been established, the CPU will read whether or not it can be sent
(not sent depending on the configuration of the Polite State transition under policy conditions).

If you can send, the following will be turned on:
Active mode: the system does not receive any synchronization signal, and RSSI low,
DLL establishment trans_slot_c, as follows:
Interrupt, to the CPU to provide 30ms interrupt.

Passive mode: the system receives the air signal, and allows the transmission,
then according to the received recv_slot_c, start building Vertical synchronization,
the generation of trans_slot_c, and according to recv_slot_c to adjust trans_slot_c,
thus providing CPU 30ms (Approximate) interrupt.

Figure 8

(Page 19)

After the establishment of synchronization, CPU will receive 30ms interrupt, the next chip by the CPU to determine the transceiver status and send and receive Type, and to provide each time slot of the DataType, PI, LCSS, send and receive type to enable, send the type of the main Have:

(middle of page 20)

4 Call control layer mode

4.1 Protocol support

Support the provisions of the agreement and the provisions of the agreement Layer3 SFID standard field control, the main services provided are:
CSBK is used to activate the BS
This process is automatically processed when the MS initiates a relay call.
Supports FNS
Feature Not Supported signaling, using Response CSBK, set the corresponding value for feedback.
Group Call
Support the use of LC to determine the way FID and FLCO framing, CCL design time slot in line with the standard Of the group call state flow, matching time slot PTT event, the channel to apply for transmission rejection, channel transmission acceptance, voice access Delayed Access Voice Receiving, PTT Release, Voice End LC Transmission, Received Idle Voice End, Non-Active Receive voice exit termination and no signal reception termination.
Individual Call
Support direct call and OACSU call; Supports CSBK establishment and CSBK feedback signal control flow of OACSU call, supports abnormal feedback signal deal with;
Unaddress voice call
Support for addressless call mode address recognition, flow control;
All call
Support for the address of all call-way recognition, process control;
Broadcast (broadcast voice call)
Support broadcast address of the call mode, process control;
Open channel call (open voice channel call)
Support Group Call and Individual Call under the OVCM mode to call and receive calls; Using the provisions of the ETSI TS 102 361-2 standard LC, PDU control word requirements, and in strict accordance with the process design, time parameters can be set, using the provisions of the agreement Polite strategy;
Data information services
Unconfirmed data transmission
(yes, the structure is ugly and barely understandable..)
Supports Rate 1/2, Rate 3/4, and Rate 1 unacknowledged message transmission and reception,
and can be set to the number according to the form,
adding a specific Header (Proprietary Header);
Confirmation information (confirmed data transmission)
Supports Rate 1/2, Rate 3/4, and Rate1 acknowledgment messages. It also supports user-defined numbers.

(page 21)

According to the form, adding a specific Header, in accordance with the agreement designed to confirm the process of sending and receiving information and exception handling;
Support variable length sliding window design;
Short Message
Support for Defined Data, Raw Data, Status / precoded Data Non-confirmed and confirmed
Transceiver mode, PDU unit data is specified by reference to the protocol;
Using the provisions of the ETSI TS 102 361-2 standard LC, PDU control word requirements, and in strict accordance with the process design
The time parameter can be set by Polite strategy stipulated in the protocol.

(still on page 21)

4.2 Instructions for use (Call Control Layer)

CCL mode base configuration includes hardware configuration and parameter configuration.
Register 0x10 is configured as b01x10xxx (binary). The main request is (? - steps are - ?) the following:

1) Group call
Group call design group frame includes Voice LC Header, Voice A ~ F, LC Terminator.
The user must configure the content: FLCO, Service Option, Group address, Source address.
User-configurable content:
    Slot: PI     LC: PF,     Mask: Voice LC Header, Terminator with LC     Access Polite policy.

5. FM compatible (Frequency modulator and demodulator ?)

FM system compatibility refers to the application for analog walkie-talkie, support voice band signal processing, including compression, decompression, Pre-emphasis and de-emphasis application technology, in full compliance with TIA / EIA-603 standard.

Figure 9
Customize FM via register 0x34, to switch filter, pre-emphasis / de-emphasis, compression / decompression features.

6. System Clock

The internal clock of the system is 49.152MHz, 9.8304MHz is provided for the DMR digital part, the FM part provides 8.192MHz, CodeC part provides 12.288MHz, while providing the external CodeC possible 24.576MHz.

Figure 10

The system clock is configured via (registers?) 0x18 and 0x19. The calculation formula is as follows:
where NO = 2 PLLDO.

Note the discrepancy in the original (chinese) datasheet.
Registers 0x18 and 0x19 are listed as 'LocalGroupAddressM' and 'LocalGroupAddressH' in chapter 2.

In an RT3, the true PLL registers (0x0B, 0x0C) contained:

[0x0b] = 0x28 = PLLM ( PLL Multiplier )

[0x0c] = 0x33 = 0b0011 0011
                  |||| \\\\_ PLL input divider,  PLLN  = 3
                  ||\\______ PLL output divider, PLLDO = 3
                  |\________ PLL 'not sleeping'
                  \_________ PLL 'in use' (not bypassed)
With XTAL=29.4912 MHz (from X201), the above 'CLK'-formula gave a wrong result:
XTAL := 29.4912MHz  =: 2.94912e+07
PLLM := 0x28
PLLN := 3
CLK  := XTAL * PLLM / PLLN / (2*PLLDO)  =: 6.5536e+07
65.536 MHz ? No way. Let's try another formula ("PLLN register value PLUS ONE", based on experience with other chips):
CLK := XTAL * PLLM / (PLLN+1) / (2*PLLDO) =: 4.9152e+07 = 49.152 MHz, q.e.d.

7. Interrupt Processing

The interrupt system consists of four interrupts, including... In normal mode, if the RF module does not need to send and receive switching configuration, then only one system interrupt on the (? .. CPU needs to be serviced ? - WB). (? Between interrupts.. - WB), You can carry out normal work processing.

1) Transceiver switching interrupt

According to the DMR standard, in the TDMA working condition, the radio frequency channel needs to carry on the unit to receive and cut 30ms Change, the conditions are generated,
the receiver generates an interrupt, in the establishment of synchronous conditions, the beginning of the 30ms transceiver For interrupt, non-fat that is received. (?)

Figure 11 : C5000 RX and TX interrupts

2) 30ms interrupt

30ms interrupts are active in the physical layer mode and data link layer mode.
The CPU uses this interrupt to decide(?) whether a time slot is transmitted, and (fills in?) the content to be transmitted.

Figure 11 b : C5000 'Time Slot' interrupt

The DMR specification ETSI TS 102 361-3, page 8, sheds some light on this.
They use the term 'frame' (60 ms) for two contiguous time slots. What ETSI calls 'frame' may be the 'superframe' in this datasheet.
3) System interrupt

The system interrupt pin is SYS_INTER. On this interrupt, the CPU reads interrupt status register 0x82, to obtain(?) 8 types of interrupts, including...
  1. Send request rejected
    This interrupt has no sub-status register, indicating that the transmit request was rejected because the channel was busy.

  2. "The transmission starts"
    Start with the sub-state register 0x84, 0x85 can be masked by the corresponding interrupt Sub-shape(?).
    The status register indicates the seven types of interrupts that generate the start of transmission, including:
    • Voice delivery
    • The OACSU request is sent for the first time
    • The OACSU request is sent a second time
    • The Vocoder configuration returns an interrupt when the AMBE3000 is configured to use the CPU.
      (HR_C5000 to the CPU to send back the configuration complete interrupt)
    • Data is sent
    • Partial retransmission of data
    • All data retransmissions

  3. "The transmission ends"
    Send the end of a sub-state register 0x86, the corresponding interrupt can be masked by 0x87 Sub-shape(?).
    State registers indicate the six kinds of interrupt generated to send end, including:
    • The voice ends normally
    • End of voice exception (transmission timeout)
    • Voice OACSU waits for a timeout
    • The data ends normally
    • Data abend (transmission timeout)
    • The data validation wait time-out

  4. "After access"
    After the access interrupt has no sub-status register, after receiving the interrupt, indicating that the access voice communication is 'After the access mode'.

  5. "Receive Data"
    The receive data interrupt has no sub-status register, but its receive data is received by register 0x51, using the DLLRecvDataType, DLLRecvCRC description of the received data type and the Wrong circumstances, CPU accordingly corresponding status display, you can also shield (? acknowledge or disable ?) the corresponding interrupt.

  6. "Receive information"
    The receive information interrupt has the sub-state register 0x90, the sub-status register has only one type, 0 indicates the whole One message reception check is passed, and 1 indicates the entire message reception check error.

  7. Abnormal exit
    Abnormal Exit Interrupts There are no sub-state registers, and the cause of the exception is an unintended internal state machine Interruption.

  8. The physical layer operates independently to receive interrupts
    Physical Layer Separate Operation Reception Interrupts: There are no sub-state registers that are generated at the physical layer in a separate operating mode.
The received data generated after the interrupt, notify the CPU to read the appropriate register to receive data.
In addition to the system interrupt, other interrupts do not need to be cleared. The system interrupt handling is as follows:

Figure 12 : System Interrupt Handler.
Branch by the bits read from register 0x82 ?

page 31

8. Data read and write

This chapter describes how to read and write registers inside the C5000 chip.
There are two SPI interfaces (SPI0 and SPI1) from the HR_C5000's point of view.
SPI0, the chip's "user interface", is connected to the STM32F405 as follows:
U_SDOPE4 PE3, "DMR_SDO"SPI0 data C5000 → STM32
U_SDIPE5, "DMR_SDI"SPI0 data STM32 → C5000
U_CSPE2, "DMR_CS"SPI0 chip select STM32 → C5000
U_SCLKPE3 PC13, "DMR_SCLK" + "PLL_CLK"SPI0 clock STM32 → C5000
In the MD380-Tools, single registers can be read via c5000peek() and written via c5000poke() in .
Their counterparts in the MD380 firmware are c5000_spi0_readreg() and c5000_spi0_writereg() .
Correction 2017-06: The MD380 circuit diagram seems to be incorrect. The 'user SPI' clock input isn't PE3 but PC13, the input data (from STM32 to C5000) is PE3, not PE4.
SPI0 and SPI1 chip is equipped with two interfaces for data read and write.
SPI0 function, including parameter configuration, the state / number
According to read and write, subsidiary parameter configuration, CMX638 parameter configuration, AMBE3000 parameter configuration, tone data writing.
It is used to read and write voice data of general vocoder.
1) SPI interface read and write timing

Figure 13 : SPI command transfer sequence

Cmd is used to identify read and write and distinguish between different functions and select Ram space.

For SPI0:

   Table 7

(no default)
  Bit 7
Bits 6..3
Bits 2..0
1:next operation is READ, 0:WRITE
see list below

For SPI1:

   Table 8

(no default)
  Bit 7
Bits 6..3
Bits 2..0
1:next operation is READ, 0:WRITE
011 indicates that the voice code voice data is operated
Addr is the initial address to be read and written at a later time, and data to be entered (or read) at a later time will start at the initial address, and Accumulated in each case, in each CS effective case, will continue to accumulate.
(in other words: The same 'address auto-increment' feature that many chips with I2C or SPI interface use.
We can read or write as many bytes in a single block as we want. Don't waste time sending register addresses)
Data0-Data'N' is the data for each read and write, the maximum length of 2048 Byte.
(page 32, we're still in the description of the SPI interfaces)

2) state control Ram data read and write
State control Ram as shown in the parameter configuration table, the address space is 0x00 ~ 0xFF, which includes the hardware parameter configuration, State control parameter configuration and interrupt information read.

3) Auxiliary parameter configuration table read and write
Auxiliary parameter configuration table is a number of very common parameters classified as ancillary parameters, including the agreement of some constant settings and Timing parameter settings, the address space is 0x00 ~ 0xFF.

4) information data read and write
The information data includes 36byte data read and write when the physical layer is working independently, the address space is 0- 35; The second floor working mode
( ? - any volunteers for working in the second floor ? )

The information data length is 9 bytes (LC), 10 bytes (CSBK, Header), 12 bytes (custom, Rate1 / 2), 19byte (Rate3 / 4) and 25byte (Rate1).
The address space for the distribution of 0 ~ 47; three working mode, the number of information according to the length of 9byte (LC), 10byte (CSBK, Header), the address space of 0 to 15, taking into account the use of double-headed Information, the maximum length of 12 bytes (PI), the address space of 16 to 27, three layers of short message data storage space Between 48 ~ 2047.
ToDo: This needs to be refactored / reformatted !

   Table 9

AddressPhysical layer modeLayer 2 modeThree-tier model
0x00~0x09Physical layer dataLCLC
CSBK, HeaderLC
Custom, Rate1 / 2spare
0x030~0x7FF  Text Message

5) The tone data is written
The tone is to use the CPU to write data through SPI0 to CodeC (built-in external can), the required cmd = 0x03, Addr = 0x00, followed by two 8bit data, write to the time interval

6) CMX638 configuration
Before configuring, wait for the configuration of CMX638 to be initialized after power on HR_C5000. When configured, HR_C5000 CMX638 can not have other operations, such as reading CMX638 encoded voice data. Through SPI0 and Cmx638 Interworking, SPI0 operation format is as follows:
Table 10 : Not translated, since there's no CMX638 in the system

7) AMBE3000 configuration
Before configuring, wait for the initialization of the AMBE3000 after the HR_C5000 is powered on.
Initial configuration includes:
Turn off the power-down mode by turning off parity on the end of the control packet.
When configured, HR_C5000 can not be used on the AMBE3000
Other operations. Through SPI and AMBE3000 interoperability, SPI operation format is as follows:

   Table 11

(1 byte)
(1 byte)
Data0 (1 byte) .... DataN (1 byte)
Write control packet0x050x00The entire control packet data
N <= 19
Read back data pack0x850x00Returns the entire packet
N <= 9 (?!)
1 write control packet if there is a return packet,
    wait for the corresponding interrupt, then you can read back the data packet.

2 Control packet written If no packet is returned,
    the interrupt is not generated.

8) SPI1 voice data read and write
The voice data will read and write from the SPI1,
the CPU in the case of voice communication,
the vocoder part of the line Parameter configuration,
through the beginning of the call and the end of the state of capture,
timing SPI1 read and write operations,
you can get harmony code (??) Consistent interfaces and data.

Figure 14

Read and write voice data operations cmd = 0x03 / 0x83, addr = 0x00.
Configuration parameters are handled via SPI0.

   Table 12

Vocoder638Bit 70: CMX638 interface off, 1: CMX638 interface on

Vocoder3000Bit 60: AMBE3000 interface off, 1: AMBE3000 interface on

DMRFromBit 50: input from VoCoder,1: input from SPI1

VocoderFromBit 4 0: represents output of the protocol layer to the vocoder,
1: represents input of the protocol layer to the vocoder,
including self-loopback and custom sounds

SPIFromBit 3 0 represents protocol layer output,
1 indicates the Vocoder output,
  protocol layer recording or vocoder recording

CodeCModeBit 2 0 means built-in,
1 means external

OpenMusicBit 1 0 for off,
1 indicates on

LocalVocoderControlBit 0 0 means that the system automatically controls,
1 indicates CPU control
ModulatorModeBit 7 0 means DMR,
1 indicates FM
Path Description:
MUX0 is controlled by [0x06] [7: 6].
where [0x06] [7: 6] cannot be equal to 2'b11,
ie CMX638 and AMBE3000 cannot be open at the same time.
(when forcedly set to 2'b11, the effect is the same as 2'b00)
MUX1 is controlled by [0x06] [5].
when = 0, MUX0 → MUX1 → SendRam0,
when = 1, SPI1_In → MUX1 → SendRam0.
MUX2 is controlled by [0x06] [4].
when = 0, DMRRecv → MUX2 → RecvRam1;
when = 1, SendRam0 → MUX2 → RecvRam1, said custom sound.
MUX3 is controlled by [0x06] [3].
when = 0, RecvRam0 → MUX3 → SPI1_Out, that's protocol layer recording,
when = 1, SendRam1 → MUX3 → SPI1_Out, that's vocoder recording.
MUX4 is controlled by [0x06] [2: 1] and [0x10] [7],
  where [0x06] [1] has the highest priority, followed by [0x10] [7].
When [0x06] [1] = 1, it means to power on, incoming call,
    SPI2 → MUX4 → InCodec / ExCodec.
When [0x06] [1] = 0, [0x10] [7] = 1, Codec → MUX4 → FM
    and FM → MUX4 → Codec
When [0x06] [1] = 0, [0x10] [7] = 0,
    Codec → MUX4 → Vocoder and Vocoder → MUX4 → Codec.

(page 35)

9. Vocoder peripheral instructions

Chip support AMBE3000 and CMX638, built-in vocoder and external optional, voice input from the Mic, through the Codec.
And then output to the vocoder through the SPI2 interface. The compressed data of the vocoder is transmitted through the multiplexed data line (McBSP / C-Bus).
Send HR_C5000 to send. Received data from the HR_C5000 through the multiplexed data lines sent to the vocoder,
vocoder will decompress the data through SPI2 to CodeC, CodeC after DA output to the Speaker.

Figure 15

Analog audio signal paths in the RT3 / MD380: Despite this 'In-CodeC' configuration, the I2S (digital audio) interface is also connected to the CPU (STM32F405) !
See also (external link) : Audio signal paths in the RT3 / MD380 and the 'baseband' chip .

10. External Codec clock

External CodeC I2S read and write clock rates can be configured via (registers? - WB) 0x30, 0x31, 0x32, 0x33.

(This was the END of the original datasheet !)

Codec clock register values read via USB from an RT3 / MD380:

 [0x30]=0x00     [0x31]=0x17     [0x32]=0x02     [0x33]=0xff
 (Mclk/BCLK,hi)  (Mclk/BCLK,lo)  (Mclk/LRCK,hi)  (Mclk/LRLK,lo)
  49.152MHz/(4*0x0017) = 534261 Hz (BCLK='bit- or bus-clock') ?
  49.152MHz/(4*0x02FF) = 16020.9 Hz (LRCK='word clock') ?
Not sure if 'LRCK' is the actual sampling rate, or two times f_sample.

Obviously 'Mclk' isn't the signal on pin 'MCLK', but the PLL'ed frequency from pin 14, 'XTAL'.
In the MD380, this pin (14) is fed with 29.4912 MHz from X201.
As explained in Chapter 6, 'System Clock', the C5000's PLL is programmed by the MD380 firmware to convert this frequency into 49.152 MHz.