[SI-LIST] : Simple load question

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From: brent.dewitt@us.datex-ohmeda.com
Date: Wed Jan 24 2001 - 14:58:19 PST


One of our engineers is very concerned about the "maximum capacitive load"
specification on a processor he's using. This is a relatively fast part with
rise and fall times on the order of 600 psec. The loads are distributed across
several memory devices, anywhere from 1 to 9 inches away. Am I correct in
thinking that if the driver sees only the capacitive component of the
transmission line impedance initially and then the "reflected capacitance" of
each input one round trip reflection time later?

Thanks,

Brent DeWitt

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