Re: [SI-LIST] : IBIS vs HSpice

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From: Mike Mayer (mwmayer@tds.net)
Date: Sat Jan 20 2001 - 06:40:46 PST


>>>>> "Ken" == Ken Wu <ken@force10networks.com> writes:

> Tony, Thanks for the reply. My understanding is that IBIS model
> uses the test-circuit(Vref, Cref and Rref) to derive the
> rising/falling waveforms and flight time of IO. SI tool vendors
> then apply the rising/falling waveforms (and probably flight
> time) to real load to figure out the IO delay(flight time). My
> question is how accurate it's going to be since the
> rising/falling waveforms are based on test-circuit instead of
> real load. Also, what do you mean the real circuit delay should
> have the test-load result substracted? Can you be a little bit
> more detail on this?

In the case of Innoveda XTK (SI simulator) and BLAST (static timing
analyzer):

The BLAST model uses datasheet values for timing, which are measured
using a specified test load (often 50pF). Even though it is one number
for min and one number for max, these delays can be thought of as the
internal delay of the part plus the delay of the I/O buffer driving
the test load:

Tdelay = Tinternal + Ttestload

XTK can recreate the testload and run a simulation to get the delay of
the I/O buffer driving the testload. This delay is put in the model as
the TIME_TO_VM parameter. When an analysis is run XTK will determine
the delay of the I/O buffer driving the real loaded trace. It creates
a file of delays to back annotate into BLAST which are the loaded
trace delay minus TIME_TO_VM:

Tback = Ttrace - Ttestload

When BLAST back annotates the delays, it adds the file numbers to the
BLAST model numbers:

T = (Tinternal + Ttestload) + (Ttrace - Ttestload)
         ^ ^ ^ ^
         | | | |
       From BLAST model From XTK simulation

  = Tinternal + Ttrace

Which is the internal delay of the part plus the delay of the I/O
buffer driving the loaded trace.

-- 
=============================================================================
Mike Mayer
mwmayer@tds.net

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