From: Jonathan Dowling ([email protected])
Date: Fri Jan 19 2001 - 16:19:05 PST
Todd,
We use a combination of behavioral and transistor level
simulation in the following manner:
1. New bus designs are first conceived in the Quad Design
XTK simulator (behavioral engine). From these initial
studies, interconnect topologies/terminations and
IO targets are generated.
2. The IO buffers are then designed to meet the required
targets for strength, edge-rate, pad parasitic, etc.
3. IO design is checked with Hspice simulations to make
sure it fits within the allowed performance range.
4. 3-D package parasitics are extracted with an internally
developed tool and coupled with Hspice process models
and w-element Tlines (2-D) for SSO simulation. On the
outside chance that the network simulation does not
converge (or takes to long to run), then linear behavioral
models are substituted for the transistor models in Hspice.
Its been my experience that IO designers appreciate having
targets rather than being faced with doing the interconnect
simulation themselves. IO targets are increasingly harder
to meet, so there is less time for IO designers to perform
adequate SI simulation. Most of their time is spent designing
PVT compensation schemes, skew minimization schemes,
optimizing for new process technologies, etc.
I'm not sure what the upper frequency limit is for this type
of design approach. Quad Design XTK in particular can be used
to model driver strength and edge-rate which is dependent on
the bit history (assuming a programmable look-up table approach).
In its present form, however, it cannot be used for modeling
drivers which adapt to feedback from the network. Other
behavioral simulators can probably be used in a similar fashion.
I would guess that 2-D Tline modeling will be obsoleted before
behavioral driver modeling.
Jonathan Dowling
AMD
--- Todd Westerhoff <[email protected]> wrote:
> Hi all,
>
> I'm curious to know who out there is running SI analysis in BOTH HSpice and
> IBIS, and what your thoughts and experiences are (good and bad).
>
> I'm most interested in the strategies people use to ensure they're
> simulating the same circuit in both simulators, how people produce/validate
> models, and how well the two sets of simulation results are expected to
> correlate.
>
> Strategies for tool use (i.e. which kind of simulation do you use for which
> part of the design cycle) would also be a good topic for discussion.
>
> Comments (both public and private) are both welcome and appreciated.
>
> Todd.
>
>
> Todd Westerhoff
> SI Engineer
> Hammerhead Networks
> 5 Federal Street
> Billerica, MA 01821
> [email protected]
> ph: 978-671-5084
>
>
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