RE: [SI-LIST] : Question

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From: Lynne Green (lgreen@mail.hyperlynx.com)
Date: Thu Oct 12 2000 - 13:49:47 PDT


The physics is the same, they just move the decimal point.

Seriously, many VLSI designers still give minimal consideration
to transmission line (inductance) effects, and even less on coupled
inductance. The lines tend to be lossy in the extreme (more RC and
Ccoupled than LC).

At ICCAD a couple of years ago there were some nice presentations
showing that including inductance could change timing significantly
on long clock nets and data buses, but had little effect on local routing
delays.

- Lynne

-----Original Message-----
From: owner-si-list@silab.eng.sun.com
[mailto:owner-si-list@silab.eng.sun.com]On Behalf Of Gary Mattingly
Sent: Monday, October 09, 2000 7:41 AM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : Question

Hello,

Does this list ever cover signal integrity
on chips as opposed to board-level signal
integrity? After watching the email over
the last two or three weeks, I do not immediately
remember seeing anything specifically oriented
toward just on-chip signal integrity, in which
I am primarily interested.

If not, is there another list that does?

Gary Mattingly

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