[SI-LIST] : RE: [SI-LIST] : A interesting questio

About this list Date view Thread view Subject view Author view

From: Peng, Smith (彭子欣) (Peng.Smith@inventec.com)
Date: Tue Sep 19 2000 - 02:48:04 PDT


Richard,
         I think it's quite difficult to guide you a workable way to
implement and solve all problems as there are many uncontrollable factors in
front of you or your group members. How many awful jobs/projects you got??
How many preparations prior to beginning SI simulation and related skill
persons ready?? (If you want to be able to assign them plenty jobs and hope
them could finish those jobs independently and on time.)
        Let me explain in detail. If you have many potential/skilled
engineers out there, then you can arrange 1~??? (??? means your headcount
vacancy.) persons to be in charge of one project. Otherwise, one engineer
needs to handle several projects. If you don't have enough skilled guys
around you, then you have to take care every projects even though there are
other engineers to be responsible for projects. If your engineers are not
familiar with HSSD/EMI, then you have to book some training courses and buy
a lot of related books for them, but it's time consuming unless you have
much time and your projects can wait for them, meanwhile, you have enough
knowledge to teach them or discuss with them. If you can get powerful SI
tools, then you have the learning curve to know how to operate and use these
tools to help you on solving SI problems. It's also time consuming. If you
run pre-route SI simulation, then you probably encounter the IBIS models and
spec problems. You need to pay many efforts to communicate with chip vendors
and try to clarify your every question. It's time consuming as well. So
let's go back the original point. How much time you have for one project??
How many qualified guys you have?? How many stuff ready, such as IBIS
models, designguides, critical issues?? If your answers are positive.
Congratulation!! You are off duty!! Just assign every guy for one project.
If they are negative, then you have to solve these concerned issues by
yourself or someone else. You know the schedule is getting delay. Sorry that
I use the question way to answer you questions. Hope it's helpful.

Best regards
Smith Peng
Email: peng.smith@inventec.com <mailto:peng.smith@inventec.com>
Tel: 886-3-3900000 ext. 2152

-----Original Message-----
From: rachild.chen [mailto:rachel.chen@huawei.com.cn]
Sent: Tuesday, September 19, 2000 8:49 AM
To: 'zanella, fabrizio'; Mayer, Mike; si-list
Subject: Re: [SI-LIST] : A interesting question

Thanks for your replies in the first.
I think the SI is a full design flow work.I built a SI group just two years
ago in our company.There is over 10,000 hardware engineers.We don't have so
much money to provide the SI analysis environment for every engineers
including the hardware and software platforms.But everybody should have some
skills in SI including some thumb rules.The layout engineers should finish
the post-layout SI analysis and EMC/EMI DRC.
SI engineers should have a system design concept.They should put out a
solution by considering every factors and finish the most difficult SI
analysis.In the same time,they should have a good balance between the
performance and the cost.This is my goal.
But by now,We don't have the system engineering design ability.Most of our
SI engineers have less practices and can't do a good system margin plan(some
things can't be simulated and only analysis by your practice datas).They are
familiar with some SI analysis tools and some a basic understanding of
transmission lines theory and timing.They can finish the net topology
analysis and finish the I/O Buffer choose and the terminal plan and the
stack-up etc.In a word, it is just a good start. I want to build a really SI
group and a good SI engineer.I think the good corporation is the first
things in different engineers.Can you tell me how to distribute the SI works
in the different engineers?What's their duties?Waiting for your suggestions.

Regards,

Rachild

----- Original Message -----
发件人: Mayer, Mike <mikem@artesyncp.com>
收件人: 'zanella, fabrizio' <zanella_fabrizio@emc.com>; Mayer, Mike
<mikem@artesyncp.com>; 'rachild.chen' <rachel.chen@huawei.com.cn>; si-list
<si-list@silab.eng.sun.com>
发送时间: 2000年9月18日 21:49
主题: RE: [SI-LIST] : A interesting question

> I assumed the question was about the goal. How to get there if you're
> starting with engineers unfamiliar with SI tools is another matter. I
know
> that Innoveda has training for XTK, BLAST, etc. and they also have a
> consulting group who will come on site, help set up the process and train
> people while helping get the first products through. I would assume that
the
> other tool suppliers have similar services.
>
>
============================================================================
> =
> Mike Mayer Artesyn Communication Products,
Inc
> Senior Hardware Design Engineer Madison, WI
> mikem@artesyncp.com http://www.artesyncp.com
>
============================================================================
> =
>
>
> > -----Original Message-----
> > From: zanella, fabrizio [mailto:zanella_fabrizio@emc.com]
> > Sent: Monday, September 18, 2000 8:40 AM
> > To: 'Mayer, Mike'; 'rachild.chen'; si-list
> > Subject: RE: [SI-LIST] : A interesting question
> >
> >
> > I'm not sure if you answered Rachild's question, Mike.
> > Rachild, if your company is in the early stages of
> > implementing SI analysis
> > for board designs, I suggest you have a group of dedicated
> > SI engineers
> > doing the analysis from pre-layout to post-layout. Have them
> > involved in
> > the various design stages and work closely with the hardware
> > designers. You
> > cannot just hand the hardware designers SI tools and expect
> > good results,
> > for most hardware designers are logic (not analog) experts.
> > Regards, Fabrizio Zanella
> > EMC Corporation
> >
> > -----Original Message-----
> > From: Mayer, Mike [mailto:mikem@artesyncp.com]
> > Sent: Monday, September 18, 2000 9:07 AM
> > To: 'rachild.chen'; si-list
> > Subject: RE: [SI-LIST] : A interesting question
> >
> >
> > For board designs of moderate complexity it is best to have
> > the hardware
> > design engineer do the SI analysis. SI is so much a part of
> > the design that
> > I don't think it is possible to do it well if it is
> > separated. SI affects
> > timing, trace topology, device selection, and many other
> > things that are
> > part of what is traditionally considered hardware design. In
> > the past, with
> > slower devices, a hardware design engineer could ignore SI
> > effects when
> > looking at these issues, but it is not possible now. The SI
> > software out
> > there is just another tool that hardware designers use to get
> > the job done.
> >
> > ==============================================================
> > ==============
> > =
> > Mike Mayer Artesyn
> > Communication Products, Inc
> > Senior Hardware Design Engineer Madison, WI
> > mikem@artesyncp.com http://www.artesyncp.com
> > ==============================================================
> > ==============
> > =
> >
> >
> > > -----Original Message-----
> > > From: rachild.chen [mailto:rachel.chen@huawei.com.cn]
> > > Sent: Sunday, September 17, 2000 8:00 PM
> > > To: si-list
> > > Subject: [SI-LIST] : A interesting question
> > >
> > >
> > > Hi everyone,
> > >
> > > It is true that everyone think SI is the most important
> > > problem in HSSD here.We know SI should be considered in a
> > > full design flow(from system level design to manufacturing)
> > > and by every engineer(hardware engineer,SI engineer,Layout
> > > engineer,ASIC engineer,EMC/EMI engineer,System
> > > enginneer,manufacture engineer etc.).I have a interesting
> > > question.What is the every engineer's duty in SI and how to
> > > distribute the SI work?
> > > For example,the pre-layout analysis should be done by
> > > hardware engineer.
> > >
> > > Waiting for your answer.
> > >
> > > Regards,
> > >
> > > rachild
> > >
> >
> > **** To unsubscribe from si-list or si-list-digest: send e-mail to
> > majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
> > si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
> > si-list archives are accessible at http://www.qsl.net/wb6tpu
> > ****
> >
>
> **** To unsubscribe from si-list or si-list-digest: send e-mail to
> majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
> si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
> si-list archives are accessible at http://www.qsl.net/wb6tpu
> ****
>
Nryȥh཮ȥ]ཊǧu隊[hȭ&ȥi˧r^=ءឲzPԔ ,X5%H$HK"͖+-v(j+zBϲ)b֫rzƫyz"nWࠚm
ࠬw

**** To unsubscribe from si-list or si-list-digest: send e-mail to
majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:29:31 PDT