**From:** *Aubrey_Sparkman@Dell.com*

**Date:** Mon Sep 18 2000 - 14:25:22 PDT

**Next message:**abe riazi: "RE: [SI-LIST] : Macromodel Creation"**Previous message:**Michael Nudelman: "[SI-LIST] : Split supply termination"**Maybe in reply to:**abe riazi: "[SI-LIST] : Macromodel Creation"**Next in thread:**abe riazi: "RE: [SI-LIST] : Macromodel Creation"

Richard,

*> ... and ultimately based on measurements.
*

If this has always been true for you, then, you've been lucky!

Aubrey Sparkman

Signal Integrity

Aubrey_Sparkman@Dell.com

(512) 723-3592

*> -----Original Message-----
*

*> From: Mellitz, Richard [mailto:richard.mellitz@intel.com]
*

*> Sent: Monday, September 18, 2000 3:50 PM
*

*> To: 'si-list@silab.eng.sun.com'
*

*> Subject: RE: [SI-LIST] : Macromodel Creation
*

*>
*

*>
*

*> All models are behavioral and ultimately based on measurements. One
*

*> behavioral model can be more accurate than another behavioral
*

*> model if you
*

*> put enough work into it. If you put more work in, it can even
*

*> be relatively
*

*> fast. Only time and money ... or is that momentum and position. :-)
*

*>
*

*> Accuracy of a single simulation may be amusing and interesting. The
*

*> application of accuracy is a statistical problem with many
*

*> parameters, only
*

*> one being the accuracy of a single simulation.
*

*>
*

*> Richard Mellitz
*

*> Intel
*

*>
*

*> -----Original Message-----
*

*> From: abe riazi [mailto:ariazi@serverworks.com]
*

*> Sent: Monday, September 18, 2000 3:10 PM
*

*> To: 'si-list@silab.eng.sun.com'
*

*> Cc: 'arpad.muranyi@intel.com'
*

*> Subject: RE: [SI-LIST] : Macromodel Creation
*

*>
*

*>
*

*> Arpad:
*

*>
*

*> Thanks for your response.
*

*>
*

*> When I wrote that SPICE transistor level models are most
*

*> accurate but also
*

*> most time consuming to simulate, I did not mean that it is
*

*> "always" true and
*

*> there can be exceptions. but it will hold true in many cases. Ron
*

*> Kielkowski (Reference 1, PP. 5 - 7) presents good
*

*> definitions and examples
*

*> in support of this point:
*

*>
*

*> 1. TRANSISTOR LEVEL MODEL: "represents devices at the most
*

*> basic simulation
*

*> level possible. In many cases, the transistor-level model is the most
*

*> accurate model possible for simulation. On the downside though, the
*

*> transistor-level model also takes the most time to simulate."
*

*> 2. MACROMODEL: " A macromodel is a collection of electrical
*

*> components which
*

*> form a simplified representation of the modeled circuit.
*

*> Many macromodels
*

*> contain dependent controlled sources to help simplify the
*

*> structure of the
*

*> model. Being simplified means that the macromodel is often easier to
*

*> construct than transistor level model, and the macromodel
*

*> often simulates
*

*> much faster than the transistor level model. But these two
*

*> elements come at
*

*> the expense of a small loss in accuracy."
*

*> 3. BEHAVIORAL MACROMODEL: "The highest level in modeling
*

*> hierarchy is the
*

*> behavioral macromodel. Behavioral macromodels contain a
*

*> collection of ideal
*

*> electrical or mathematical components. Often behavioral
*

*> macromodels contain
*

*> a collection of ideal electrical or mathematical components
*

*> which are used
*

*> to describe a function of the circuit. Being at the top of
*

*> the hierarchy
*

*> means the behavioral model usually simulates faster than any
*

*> other type of
*

*> model, but often this increased speed comes from a loss in accuracy".
*

*>
*

*> As an example, the transistor level model of an Op Amp can
*

*> have about 19
*

*> transistors (plus some passive components), the macromodel
*

*> of the Op Amp
*

*> consists of only two transistors and four diodes (plus some passive
*

*> components and dependent controlled sources). The Op Amp
*

*> behavioral model
*

*> contains much simpler input and output blocks.
*

*>
*

*> Based on above definitions and examples, in many cases the
*

*> transistor level
*

*> models are the most complex (and accurate representation of
*

*> the device) but
*

*> at the price of being most time consuming to simulate.
*

*>
*

*> Best Regards,
*

*>
*

*> Abe
*

*>
*

*> -----Original Message-----
*

*> From: Muranyi, Arpad [SMTP:arpad.muranyi@intel.com]
*

*> Sent: Monday, September 18, 2000 10:36 AM
*

*> To: 'abe riazi'; 'si-list@silab.eng.sun.com'
*

*> Subject: RE: [SI-LIST] : Macromodel Creation
*

*>
*

*> Abe,
*

*>
*

*> I would like to comment on the three bullets you listed which
*

*> put accuracy
*

*> and speed into an inverse relationship regarding transistor level and
*

*> behavioral models. Simply said this general relationship is NOT TRUE.
*

*>
*

*> You CAN model devices to even a higher level of accuracy behaviorally
*

*> than on a transistor (SPICE) level if you like. It all
*

*> depends on what
*

*> parameters you use and what goes into the behavioral model. And this
*

*> increased accuracy does not mean that your model will
*

*> automatically get
*

*> slower.
*

*>
*

*> Take a transistor, for example. You can describe it with its
*

*> geometry,
*

*> and properties of the materials that it is made from. A
*

*> SPICE tool then
*

*> converts all that information to electrical characteristics.
*

*> This takes
*

*> a lot of equations and calculations. On the other hand, you
*

*> can describe
*

*> the same transistor's characteristics by providing its node
*

*> voltage and
*

*> current relationships directly (with tables, equations,
*

*> transfer functions,
*

*> etc...) which CAN reduce the number of calculations SPICE has
*

*> to do, making
*

*> it faster.
*

*>
*

*> Now think about the underlying model equations SPICE uses
*

*> when you do it
*

*> the conventional SPICE way. You can have a LEVEL=3 or BSIM4 set of
*

*> equations. Which one is more accurate? Most likely the BSIM4, since
*

*> it is more recent. However, if your behavioral transistor model DOES
*

*> describe something that even BSIM4 cannot, you behavioral
*

*> model will be
*

*> even more accurate. Yet this does not mean that it has to become
*

*> automatically slower.
*

*>
*

*> What I wanted to illustrate here is that the accuracy of the
*

*> model depends
*

*> on what goes into it. It's speed, however, depends on how
*

*> the device is
*

*> described. These two are not as strongly related as your three points
*

*> suggest.
*

*>
*

*> Arpad Muranyi
*

*> Intel Corporation
*

*> ==============================================================
*

*> ==============
*

*>
*

*>
*

*> -----Original Message-----
*

*> From: abe riazi [mailto:ariazi@serverworks.com]
*

*> Sent: Friday, September 15, 2000 7:17 PM
*

*> To: 'si-list@silab.eng.sun.com'
*

*> Subject: [SI-LIST] : Macromodel Creation
*

*>
*

*>
*

*>
*

*> Dear Scholars:
*

*>
*

*> While visiting a Barnes & Noble bookstore in San Jose, I
*

*> purchased a copy of
*

*> the "Spice Practical Device Modeling" , by Ron Kielkowski.
*

*> What especially appealed to me about this publication was its
*

*> high emphasis
*

*> on model creation. In this book SPICE models are classified
*

*> according to a
*

*> hierarchy which includes:
*

*>
*

*> 1. Transistor-level models ( provide highest accuracy,
*

*> though most time
*

*> consuming to simulate).
*

*> 2. Macromodels.
*

*> 3. Behavioral Macromodels (fastest to simulate, but least accurate)
*

*>
*

*> Most attention is devoted to Macromodels, because they offer
*

*> a practical
*

*> level of accuracy (less than 5% rms error over operating
*

*> range) and can be
*

*> created in a reasonable amount of time (less than eight hours).
*

*>
*

*> The procedure recommended by Ron Kielkowski for construction
*

*> of macromodels
*

*> consists of the following steps:
*

*>
*

*> i. Review the datasheet to obtain as much information related to model
*

*> creation as possible (although, frequently majority of the
*

*> information given
*

*> in the datasheet has little value towards model generation).
*

*> ii. Utilize bench-top measurement equipment to produce I-V,
*

*> C-V and Z-F
*

*> curves.
*

*> iii. From above data extract the desired model parameters.
*

*>
*

*> For a resistor, the Macromodel elements consist of a nominal
*

*> resistance
*

*> Rnom and a parallel capacitance Cp; for an inductor, Lnom (nominal
*

*> inductance), Rs (coil resistance) and Cp (winding
*

*> capacitance); and for a
*

*> capacitor, Cnom (an ideal capacitor), RL (leakage resistor),
*

*> Ls (series
*

*> inductor) and ESR (electrical series resistance). These
*

*> macromodels are
*

*> illustrated by Figure 1 (attached gif picture).
*

*>
*

*> In this publication (reference 1), the significance of impedance vs.
*

*> frequency plots is emphasized, because:
*

*>
*

*> a. Regarding macromodel of a resistor, the |Z| vs. F graphs aid to
*

*> ascertain Cp.
*

*> b. For inductor Macromodels, they allow determination of the series
*

*> resistance frequency (Frs) and self resonating frequency
*

*> (Fsrf) from which
*

*> values of Lnom and Cp can be calculated via simple formulas.
*

*> c. Considering capacitor macromodel, several parameters can
*

*> be extracted
*

*> from the impedance vs. frequency curves, such as ESR (RS) ,
*

*> lead inductance
*

*> Ls (calculating Ls involves Fsrf which can be obtained from
*

*> graph) and Cnom
*

*> (the nominal capacitance can be also measured by means of a
*

*> low frequency
*

*> capacitance meter).
*

*>
*

*> ESR and |Z| vs. F plots have been explained previously in
*

*> this forum in
*

*> relation to PCB power distribution systems, decoupling and bypass
*

*> capacitors. They are also included here due to their
*

*> significance towards
*

*> macromodel generation.
*

*>
*

*> Figure 2 presents two examples of impedance vs. frequency
*

*> graphs. Such plots
*

*> can be created in a number of different ways; here, Microsoft
*

*> Excel was
*

*> employed. In each case the raw data consisted of three
*

*> columns: current ( I
*

*> ) , Voltage drop ( V ) and frequency ( F ). The Excel
*

*> program calculated
*

*> another data column (impedance Z = V/I ), and produced the
*

*> logarithmic
*

*> impedance plots. Clearly, ESR strongly influences the shape
*

*> of |Z| vs. F
*

*> curves.
*

*>
*

*> Macromodels can be incorporated into SPICE simulation files
*

*> as subcircuits;
*

*> demonstrated by the example below:
*

*>
*

*> Example 1. Encapsulation of a capacitor macormodel CMACRO, having
*

*> parameters Cnom, RL, Ls and Rs (ESR).
*

*> In the circuit input file example.cir:
*

*>
*

*> X_MACRO 2 0 CMACRO
*

*> .INCLUDE EXAMPLE.MOD
*

*>
*

*> In the model file example.mod:
*

*>
*

*> .SUBCKT CMACRO 10 20
*

*> Cnom 10 30 1000uF
*

*> Rs 30 40 0.15ohms
*

*> Ls 40 20 5nH
*

*> RL 10 30 10meg
*

*> .ENDS CMACRO
*

*>
*

*> Use of macromodels instead of SPICE primitive models can
*

*> significantly
*

*> enhance the accuracy of a high frequency simulation and yield
*

*> results in
*

*> excellent agreement with physical measurements.
*

*> Simulation of certain cases (such as high power circuits)
*

*> require taking
*

*> into consideration effects due to temperature variations. Temperature
*

*> dependent macromodels can be readily constructed (reference 1).
*

*>
*

*> To summarize, Macromodels assume an intermediate position in
*

*> the hierarchy
*

*> of SPICE models in the sense that they are below the
*

*> transistor-level models
*

*> in accuracy and rank second to behavioral models in
*

*> simulation speed. They
*

*> are in demand by being practical; i.e., can be created in a reasonable
*

*> amount of time with an error margin tolerable in many applications.
*

*> Impedance vs. frequency plots play a critical role in creation of
*

*> macromodels of passive components. These models can be
*

*> inserted into SPICE
*

*> input files as subcircuits. Simulations utilizing macromodels
*

*> yield superior
*

*> results than using ideal SPICE primitives, particularly in the high
*

*> frequency domain.
*

*>
*

*> Reference 1. R. M. Kielkowski, "SPICE Practical Device Modeling",
*

*> McGraw-Hill, Inc. 1995.
*

*>
*

*> Thanks for your comments and with best regards,
*

*>
*

*> Abe Riazi
*

*> ServerWorks
*

*> 2251 Lawson Lane
*

*> Santa Clara, CA 95054
*

*>
*

*>
*

*>
*

*>
*

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**Next message:**abe riazi: "RE: [SI-LIST] : Macromodel Creation"**Previous message:**Michael Nudelman: "[SI-LIST] : Split supply termination"**Maybe in reply to:**abe riazi: "[SI-LIST] : Macromodel Creation"**Next in thread:**abe riazi: "RE: [SI-LIST] : Macromodel Creation"

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