Re: [SI-LIST] : inductance extracted by ansoft SI3D

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From: Scott McMorrow (scott@vasthorizons.com)
Date: Mon Jul 17 2000 - 15:41:35 PDT


Ali is correct.

A 0.236 via is a structure that will have around a
40 to 50 ps delay which may or may not act as
a stub, depending upon the structure of the pad stack
and the entry and exit layer of traces from the via. It
is even quite possible that you might inadvertently create
some very good quarter wave resonators at a harmonic
of the switching frequency that will degrade your overall
jitter budget.

Antipad size will have a significant effect on the overall
via capacitance and impedance, as will the size and
number of via pads. Removal of unused pads will
also vary these characteristics, as will counterboring
the via barrels.

I'd opt for a test board with each possible via configuration
and make measurements with the actual driver being used
in the real circuit. I'd also suggest FDTD analysis to
corroborate the measurements. This will take some time to
setup and some significant computation time and
memory resources, but the results will be worth it.

regards,

scott

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com

Hassan Ali wrote:

> > > Doug, > > That was a simplified sketch of via on a 24-layer pcb, 0.235" thick and has to operate at 2.5GB/s, 100ps risetime. Probably that > equivalent circuit was an overkill, but how do I know that, and what would a simplified version be? > > Thanks. > > Hassan. > > -----Original Message----- > From: Doug McKean [mailto:dmckean@corp.auspex.com] > Sent: Monday, July 17, 2000 4:43 PM > To: si-list@silab.eng.sun.com > Subject: Re: [SI-LIST] : inductance extracted by ansoft SI3D > > Hassan, maybe a question to ask is ... > > What is going to be the effect on signal integrity > of an .062" (?) long discontinuity of some magnitude > somewhere along on the trace? Perhaps it may be > insignificant. > > It seems as though the equivalent circuit presented is > attempting to model some 3rd order analysis of a via. > I might suggest that in order to do 3rd order analysis, > the assumption that all associated grounds are perfect > and identical may be something to reconsider. On the > other hand, it may be perfectly sufficient for your > purposes. > > Unintended assumptions can kill ya every time ... > > Just my 2 cents. > > - Doug McKean > > **** To unsubscribe from si-list or si-list-digest: send e-mail to > majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE > si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. > si-list archives are accessible at http://www.qsl.net/wb6tpu > ****

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