[SI-LIST] : Job Opening at Teradyne in Southern California

About this list Date view Thread view Subject view Author view

From: Marc Rich (Marc_Rich@notes.teradyne.com)
Date: Wed May 24 2000 - 14:02:55 PDT


My Signal Integrity and PCB Engineering group has an opening for an experienced
signal integrity engineer.

Teradyne does research, design, and development of high-performance
semiconductor test
systems. We are currently developing systems for testing VLSI devices operating
in the
1 - 2 GHz range. We need to provide timing measurement accuracy in the <100 Ps
range
and voltage measurement accuracy in the mV range, so signal integrity is key to
our
success.

Teradyne is a well-established and highly successful company, with record sales
and profits both
last year and in the current quarter. The VLSI Test Division is in Agoura
Hills, CA,, located between
Los Angeles and Santa Barbara.

Here is the job description:

FUNCTIONS:
- Perform signal integrity analyses for high speed signals including timing,
crosstalk, ground
bounce, and power quality.
- Design and develop technology for printed circuit boards, connectors, back
planes, cables and
systems.
- Create reference guidelines and designs, and develop termination strategies.
- Work with ASIC designers on I/O driver requirements, interface timing and
optimization of
device pinout.
- Design prototype test boards for correlating with simulation data.
- Measure crosstalk, ground bounce, and reflections at component, board and
system levels.
- Review designs for EMC compliance.

SKILLS:
- BS, MS, or PhD in EE, with at least 5 years experience in signal integrity.
- Skill in SI modelling, field solver and other simulation tools, such as
HSPICE, IBIS models,
XTK, Speed97, etc.
- Skill in UNIX and Windows.
- Skill in layout and schematic entry tools such as Allegro and Concept.
- Skill in TDR and VNA measurement techniques, spectrum analyzers, and other lab
equipment.
- Experience with high performance I/O technologies such as SSTL and LVDS.
- Experience characterizing parts and boards in a lab environment.
- Knowledge of signal integrity issues such as: ground bounce, noise margins,
impedance
matching, transmission lines, cross talk, and bypassing.
- Good communications skills.
- Experience in ATE is a plus.

Please contact me directly if you are interested in this position.

Marc Rich, PhD
Hardware Engineering Manager
VLSI Test Division
Teradyne, Inc.
30801 Agoura Road
Agoura Hills, CA 91301

818.874.7586
marc.rich@teradyne.com

**** To unsubscribe from si-list or si-list-digest: send e-mail to
majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Wed Nov 22 2000 - 10:50:28 PST