Re: [SI-LIST] : LVDS SSO Analysis Question.

About this list Date view Thread view Subject view Author view

From: David Haedge (d-haedge@raytheon.com)
Date: Fri Nov 05 1999 - 11:44:35 PST


.

Christian/D. C.,

The currents are current *increases* causing voltage drops on the core
voltage.
The currents appear to be of a 'crowbar' nature in the predriver, i.e.
the VDD
spikes come right through to the VSS node with little or no distortion.
This
does lend itself to pairing VDD and VSS nodes and creating as high a
mutual
term as possible to cancel out the self inductances, thereby minimizing
core
voltage droop and groundbounce. My first cut at this was just using an
estimate of the self inductance of the bondwires for VDD and VSS. I'll
add the mutual term and see what happens.

Thanks,

David Haedge
Raytheon

P.S. It is interesing to get all of those "Out of Office" replies from
the
various members of the list. You can learn a few things.

"Christian S. Rode" wrote:
>
> D. C.:
>
> A question: Is it really practical to assume the benefits of reduced
> package crosstalk with push-pull drivers? I can see that you could
> tune the delays in open-collector-like technologies to maintain
> a nearly continuous current flow (at least in the nominal case) but
> with CMOS drivers and cross-coupled break-before-make pre-drivers
> won't you always get a period where both drivers are off?
>
> The spike in that case would be due to currents dropping, rather
> than increasing and creating an initial on-chip voltage rise, rather
> than a fall. David didn't characterize the nature of his spikes.
> David?
>
> Chris Rode
>
> "D. C. Sessions" wrote:
> >
> > David Haedge wrote:
> > >
> > > Fellow SIers,
> > >
> > > I am working on an SSO analysis that involves large numbers of LVDS outputs
> > > switching on a die. One of the reasons to use LVDS is because the driver is
> > > basically just redirecting a 4mA current in the output loop, hopefully
> > > eliminating large di/dt's on power and ground. However, my SPICE analysis
> > > shows a 20-25mA current spike on VDD and VSS with a rise/fall time of about
> > > 230ps each time the device switches (375MHz rate). It was assumed that we
> > > could get by with a lot less VDD and VSS pads due to the expected low di/dt's.
> > > It appears now that with this large unexpected current spike, we need to triple
> > > the number of powers and grounds to achieve an acceptable voltage drop/ground
> > > bounce. Has anybody out there seen this sort of behavior in LVDS circuitry?
> > > Or is this just perhaps a quirk in SPICE (or my chosen vendor)?
> >
> > Assuming that you're not running the predriver on the output rails (BAAAAAD idea)
> > then it sounds like you have some rise/fall assymetry. Step one is to fix it,
> > since power noise is the least of the troubles it causes.
> >
> > Beyond that, you may not have a big problem Oddly enough, in a differential
> > current environment supply inductance can actually be a Good Thing since it
> > effectively forces rise/fall symmetry. Put some package inductance into that
> > simulation (with or without mutual inductance, although ignoring mutual
> > inductance is kinda silly) and see what happens. Betcha you like the results.
> >
> > --
> > D. C. Sessions
> > dc.sessions@vlsi.com
> >
> > **** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****
>

**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Tue Feb 29 2000 - 11:39:39 PST