Re: [SI-LIST] : LVDS SSO Analysis Question

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From: Alaa Alani (alaa@lsil.com)
Date: Fri Nov 05 1999 - 11:50:26 PST


David,

I 've done some sso analysis on lvds before and came to the conclusion
that
the spikes caused by sso are not proportional to the sso number. These
are
usually very narrow spikes on the power and ground rails, and have very
little
impact (ground bounce and power droop). However, what I was concerned
about
was the pulse width jitter on the switching line. AS the sso number
increases,
you will notice higher PWJ which may lead to some timing problems. This
is
because these spikes can cause variable delay in the switching signal
which can
be easily measured by veiwing the eye diagram of your signal.

Alaa Alani
LSI Logic
UK

> X-Unix-From: d-haedge@raytheon.com Wed Nov 3 19:58:24 1999
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> Date: Wed, 03 Nov 1999 12:46:07 -0600
> From: David Haedge <d-haedge@raytheon.com>
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> To: si-list@silab.eng.Sun.COM
> Subject: [SI-LIST] : LVDS SSO Analysis Question
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> Fellow SIers,
>
> I am working on an SSO analysis that involves large numbers of LVDS outputs
> switching on a die. One of the reasons to use LVDS is because the driver is
> basically just redirecting a 4mA current in the output loop, hopefully
> eliminating large di/dt's on power and ground. However, my SPICE analysis
> shows a 20-25mA current spike on VDD and VSS with a rise/fall time of about
> 230ps each time the device switches (375MHz rate). It was assumed that we
> could get by with a lot less VDD and VSS pads due to the expected low di/dt's.
> It appears now that with this large unexpected current spike, we need to triple
> the number of powers and grounds to achieve an acceptable voltage drop/ground
> bounce. Has anybody out there seen this sort of behavior in LVDS circuitry?
> Or is this just perhaps a quirk in SPICE (or my chosen vendor)?
>
> Anxiously awaiting replies,
>
> David Haedge
> Raytheon
>
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