From: [email protected]
Date: Thu Nov 04 1999 - 23:22:47 PST
Unfortunately the skew among output pins are presumably random
that I wonder the adjustable delay line compensation would be
a good choice for mass production. It is true that there is
certain skew pattern at the output pins for a specific IC design
yet it is not garanteed.
I have thought about a clock management chip with internal
PLL that can help to minimize the skew, but I can't figure out
anything which can run up to 240MHz.
---------------------- Forwarded by Raymond Leung/QSA/AU on 05/11/99 17:19
Jason Zheng <[email protected]> on 05/11/99 15:47:17
Please respond to [email protected]
To: [email protected]
cc: (bcc: Raymond Leung/QSA/AU)
Subject: Re: [SI-LIST] : [Fwd: Majordomo results: Looking for highspeedbuffer
> Steve is right that the part is not fast enough for you. Besides, you may not
> be happy with 500ps skew among the outputs
Thank you for your reply!
Our ASIC is done already that needs 240 Mhz clock input.
We are designing the prototype board for them. We plan to
have adjustable delay lines to manage the skew. The key
is to find a part that is fast enough to drive 100 or 50 ohm
transmission line at TTL/CMOS levels. If you know of any part
that may do it in normal temperature condition, please let me
know. This prototype board does not need to work at worst temperature
conditions; will be just the room temperature.
thanks in advance!
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