RE: [SI-LIST] : XTK multiboard simulation using amp spice connect or models....... ..

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From: Marc Humphreys (mhumphreys@nexabit.com)
Date: Thu Dec 02 1999 - 06:30:46 PST


Slightly off the topic but relevent to hierarchical simulation process

Another way to control the scope of the simulation in a hierarchical design
is
by adding the following line to you GCF control section.

CONTROL
# HIERARCHY_MODE = SINGLE_BOARD | FULL_SYSTEM | MASTER_PLUS_IO | IO_ONLY
    HIERARCHY_MODE = IO_ONLY

This will save you time, disk space, build time etc. if you simply want to
analyze those signals
that cross a connector boundary.

---------------------------------------------------------------------
Marc Humphreys
Lucent Technologies
Core Routing - InterNetworking Systems
508-460-3355 x236
e-mail: marchumphreys@lucent.com
--------------------------------------------------------------------

CONTROL
# HIERARCHY_MODE = SINGLE_BOARD | FULL_SYSTEM | MASTER_PLUS_IO | IO_ONLY
    HIERARCHY_MODE = IO_ONLY

> -----Original Message-----
> From: Abe Riazi [SMTP:ariazi@anigma.com]
> Sent: Wednesday, December 01, 1999 11:00 PM
> To: 'si-list@silab.eng.sun.com'
> Subject: RE: [SI-LIST] : XTK multiboard simulation using amp spice
> connector models....... ..
>
>
> Syed Huq Wrote:
> >
> >Then use a hdf and con file to define the hierarchy of boards connecting
> >to each other and the 'mapping' of the connections(con file). This con
> file
> >describes how the nets get tied across the connector.(See examples in Ch7
> of
> >'Preparing PCB database for simulation with TLC/XTK/QUIET').
> >
> >Then follow the translation process and it's a piece of cake.
> >
> >% tmp -hdf <design>.hdf
> >% isf2xtk -hdf <design>.hdf
> >
> >Regards,
> >Syed
> >Cisco Systems, Inc
>
> Hi Syed:
>
> Let me add that when creating connection files careful attention
> should be paid to the pin names of the mating connectors, in order to
> determine if any swap files are required (which then needs to be
> specified in the .con file). Furthermore, when carrying out multi-board
> hierarchical simulation, it is advisable to create a Net file (,net) to
> limit the system simulation only to those nets or buses of interest,
> thereby enhancing the simulation efficiency. I have discovered that the
> TMP program has some important limitations when executed in conjunction
> with a Net file. However, ISF2XTK cooperates well with .net and
> generates a Topology file containing only those nets dictated by the Net
> file.
>
> Best Regards,
>
> Abe Raizi
> Anigma, Inc.
>
>
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