From: David Haedge ([email protected])
Date: Fri Nov 19 1999 - 13:57:52 PST
Fellow SIers,
I have an ASIC vendor that claims that *each* VDD bond pad on the die forms a
capacitor of over 200pF, referenced to the VSS rail. There is virtually no
inductance to overcome, so my SPICE simulations show almost no voltage droop
under worst case SSO switching. My question is: Is this capacitance number
real and, if so, how is it achieved? I would like to believe these numbers,
but I'm skeptical. Has anybody out there seen or measured this large of a
capacitance in any of today's silicon technologies?
David Haedge
Raytheon Company
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