RE: [SI-LIST] : Die Power Pad Capacitance

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From: Weber Chuang (WeberChuang@via.com.tw)
Date: Sun Nov 21 1999 - 21:47:26 PST


Hi Si-gurus,

  In our current product, we implement the gate oxide capacitor to stable
the power/ground system, but from some detailed simulation, we found
interesting phenomenum, once the en pin of a I/O is turned on, then the
output pin is either charged to high or low state, and at this moment, we
found that the package inductance and the gate capacitor start to oscillate.
Unless the cap is large enough, or it seems to corrupt the power/ground
system. Do you have any comment on this?
   

  Best Regards
    Weber Chuang
 Signal Integrity Engineer,
 VIA Technologies, Inc. Taipei, Taiwan, ROC
 TEL : 886-2-22185452 ext : 6522
 mailto:weber@via.com.tw
 http://www.via.com.tw
 Very Innovative Architecture

-----Original Message-----
From: Sandy Taylor [mailto:cmos@rockisland.com]
Sent: Saturday, November 20, 1999 7:27 AM
To: si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : Die Power Pad Capacitance

David Haedge wrote:

> I have an ASIC vendor that claims that *each* VDD bond pad on the die
forms a
> capacitor of over 200pF, referenced to the VSS rail.

David

Using gate oxide for a decoupling capacitor in the region of the pad
in a generic 0.6u process you would have about 3.7fF/u**2.
So 200pF would be square 232u on a side. That could be done.
In a more modern process it would be easy.

The last microprocessor I worked on had well over 100 nF (total)
decoupling between VDD and VSS.

If your ASIC is in a technology below 0.6u, then I would believe 200pF.

This will help you mitigate the internal collapse of the power supply,
but if most pins switch in the same direction, you can still suffer
from the package inductive effects.

Sandy Taylor
CMOS Solutions

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