RE: [SI-LIST] : ripple on the power and ground rail

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From: Larry Miller (ldmiller@rhapsodynetworks.com)
Date: Tue Apr 17 2001 - 19:51:16 PDT


When IEEE 802.3z was considering a 125 MHz parallel interface (GMII) the
fellow that was working on it actually opened up an IC and measured the
signals at the chip. The differences between that and what could be seen
outside the chip were dramatic.

Consequently, the IEEE standard does not specify the signal characteristics
other than to spec a template within which the signals (as measured outside
the package) may fall, and it is up to the IC vendor to (somehow) guarantee
that the correct response inside the package is obtained.

Subsequent experience with custom ASICs showed that this is really a
non-trivial situation. The technical terminology was "clutching the
gunny"....

Having said that, it sounds like you are talking about AC at power supply AC
mains and switching frequencies which would probably be at low enough
frequencies to not cause "ground bounce" as the term is generally used.

If you modulate the Vcc or Vdd at a high enough amplitude you will indeed
see amplitude modulation on the logic outputs, and probably other
interesting effects and phenomena as well. CMOS can be fairly resilient over
a wide voltage range, since the logic levels are (within reason) percentages
of Vdd.

-----Original Message-----
From: Saeen Malik [mailto:saeens@hotmail.com]
Sent: Monday, April 16, 2001 5:15 PM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : ripple on the power and ground rail

Hello Gurus,

Is there a way to estimate the power/ground bounce inside the chip
i.e. before the package parasitics. I have run some simulations but now
I want to correlate the results using measurements.

Secondly, I always thought that the power supply ripple would appear
on the signal while driving high e.g. if there is a dip in the supply there
should be a corresponding dip in the output signal. Well my measurements do

not indicate that. Am I missing something?

Saeen
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