RE: [SI-LIST] : internal timestep too small in transient analysis

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From: Aubrey_Sparkman@Dell.com
Date: Mon Mar 26 2001 - 09:35:24 PST


Elias,
In addition to the ones Kim listed, some of my favorite options (but for a
different spice) to try are:
.options gmin=1e-9
.options ABSTOL=1e-9
.options VNTOL=1e-3

And believe it or not, try a smaller timestep in your .tran statement!
.tran 10ps 35ns 5ns

Sometimes their isn't enough REAL loss modeled in the circuit and the
simulator can't resolve the fast changes or noise/ringing.

Aubrey Sparkman
Signal Integrity
Aubrey_Sparkman@Dell.com
(512) 723-3592

> -----Original Message-----
> From: Kim Helliwell [mailto:khelliwe@acuson.com]
> Sent: Monday, March 26, 2001 11:07 AM
> To: Elias Lozano
> Cc: si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : internal timestep too small in transient
> analysis
>
>
> > Elias Lozano wrote:
> >
> > I have a question,
> >
> > I am having a lot of trouble with this error when doing
> signal integrity simulations of some I/O buffers with package
> > models and T models for tranmission lines as well as some
> loading. I am using HSPICE2000 version. I will change to U
> > and then W models for more accuracy.
> >
> > I would like to get a fresh look at what are the best
> options to use when having this problem.
> > In the past, I have had the same problem with TSMC 0.18um
> models due to some negative-mos conductances?
> > Is there anyone out there experiencing the same problem and
> if so any ideas on how to find the right set of options so
> > that I don't get these erros?
> >
> > Once again this is what I am simulating:
> >
> >
> > I/O buffer + Package model + Tmodel + capacitive loading
> >
> > I appreciate any comments.
> >
> > Regards
> >
> > Elias
>
> If you are getting TSTS errors with the IBIS buffers, this probably
> means there is a problem with the buffer model. TSTS errors
> are mostly
> associated with MOS models because of the large dynamic range of
> conductances and the difficulty in insuring that the
> capacitance models
> are continuous across the piecewise boundaries. Negative capacitances
> might do it, too!
>
> Here are the steps I would take: I would get in touch with
> the HSPICE hotline
> (800.346.5953) and tell them of the difficulties you are
> experiencing, and
> get them to take a look at your circuit; they very well may
> find a bug in
> the IBIS model code as a result.
>
> Meanwhile, the options that help (about 30% of the time) in
> solving TSTS
> problems are:
>
> Increase ITL4 to 100 (if it isn't already there)
> Increase RELTOL to .01 (no larger than that!)
> Set BYPASS=0 (don't allow bypassing)
>
> A perusal of Chapter 8 of the HSPICE manual might turn up
> other options
> that would help, but the ones above are what I'm familiar
> with from other
> simulators. The person answering the phone at the hotline
> might be able
> to suggest other options to try.
>
>
> --
> Kim Helliwell
> Senior CAE Engineer
> Acuson Corporation
> Phone: 650 694 5030 FAX: 650 943 7260
>
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