[SI-LIST] : Signal Integrity position at HP Fort Collins, CO

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From: Tim L. Michalka (tim@fc.hp.com)
Date: Thu Mar 08 2001 - 07:30:31 PST


HP's Systems VLSI Technology Operation has an immediate opening in
Fort Collins, Colorado for a signal integrity engineer in the area of
packaging and interconnection. This person will be part of a highly
skilled Electrical Structures & Signals team performing package and
board level design and signal integrity analysis for high performance
CPU and CEC chips.

The team is part of the organization that has been responsible for
delivering industry leading RISC performance breakthroughs since HP
introduced its first Precision Architecture (PA-RISC) computer systems
in the mid-80's. While exciting design work continues to keep the
PA-RISC architecture an industry leader, SVTO is also answering the
challenge for the future, post-RISC computing world. For example, SVTO
collaborated with Intel on the development of the second IPF
processor, also known as McKinley.

Teamwork, initiative, innovation and appropriate risk-taking are
emphasized by this highly motivated and successful design team.

Essential Responsibilities:

Key deliverables for this position are: package and board level design
and physical layout, electrical model creation for interconnection and
power delivery systems, electrical signal simulation & analysis, and
promote teamwork within the team and across team boundaries. The
engineer will work closely with chip design teams, system designers,
and manufacturing engineers optimize system design and performance,
and to meet physical and reliability requirements of the end
product. The engineer will also have the opportunity to evaluate and
develop new tools and techniques to maximize the efficiency with which
new systems are developed.

Skills/Knowledge Qualifications:

Musts:

* BSEE or related discipline.
* 2 years experience in electronics packaging & interconnect
* Basic understanding of the materials, physics, and electronic
principles of packaging and interconnection technologies.
* Good teamwork and organization skills.
* Strong verbal and written communication skills are essential.

Desired:

4 years Experience in package and board design and manufacturing, or
chip I/O
design
Experience performing bus simulations and measurements for signal
integrity
Experience with package & board CAD tools (particularly Cadence)
Experience with SPICE
Experience with RLCG parameter extraction tools
Experience programming with Perl or C

For further information contact:
 
Tim Michalka TEL: 970-898-3555
Hewlett-Packard Company FAX: 970-898-3961
3404 East Harmony Road MS 32 e-mail: tim_michalka@hp.com
Fort Collins, CO 80528-9599

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