RE: [SI-LIST] : Simulation of address and data bus

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From: Greim, Michael (mgreim@sonusnet.com)
Date: Thu Mar 08 2001 - 06:18:15 PST


If in fact you are in a SDR application, then your maximum
toggle rate for the signal would be half the clock frequency,
however, one must exercise care to make sure that the signal
displays appropriate behavior at the time that it will be
sampled which is at the 166 rate in this case. Simulation at
the clock frequency may give you eroneous data in that you only
have half the time available before the waveform starts heading
in the other direction. With a heavily loaded etch or weak
drive, this may manefest itself as a waveform that has a hard
time getting to/beyond threshold. Increasing the period can sometimes
have a magical effect in curing this apparent problem.

just my 0.02

Best Regards,

Michael C. Greim Sonus Networks
mgreim@sonusnet.com 978-589-8336

Making the world safe for digital signals everywhere

And all this science I don't understand
It's just my job six days a week

The time is gone. The email's over
Thought I'd something more to say......

-----Original Message-----
From: Patel, Bhavesh [mailto:bpatel@cyras.com]
Sent: Wednesday, March 07, 2001 11:05 PM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : Simulation of address and data bus

Hi! I had a question regarding simulations of address and data bus at
particular frequencies. Say, if the chip is being clocked at 166Mhz do we do
simulations of the address and data bus to the chip at 166Mhz or do we do it
at half the clock frequency.? What would give an approx real world scenario,
simulation at the clock frequency or half the clock frequency?

Thanks
Bhavesh

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